Wireless power transfer is commonly realized by means of near-field inductive coupling and is critical to many existing and emerging applications in biomedical engineering. This paper presents a closed form analytical solution for the optimum load that achieves the maximum possible power efficiency under arbitrary input impedance conditions based on the general two-port parameters of the network. The two-port approach allows one to predict the power transfer efficiency at any frequency, any type of coil geometry and through any type of media surrounding the coils. Moreover, the results are applicable to any form of passive power transfer such as provided by inductive or capacitive coupling. Our results generalize several well-known special cases. The formulation allows the design of an optimized wireless power transfer link through biological media using readily available EM simulation software. The proposed method effectively decouples the design of the inductive coupling two-port from the problem of loading and power amplifier design. Several case studies are provided for typical applications.

SUMMARYIn-building power lines have often been considered as attractive media for high-speed data transmission, particularly for applications like home networking. In this paper, we develop models for power line channels based both on theoretical considerations and practical measurements. We consider power line channel frequency response and noise models in the 1-30 MHz band and propose a number of power line test channels in which to measure the performance of power line modems.

This paper presents several techniques for the very large-scale integration (VLSI) implementation of the maximum a posteriori (MAP) algorithm. In general, knowledge about the implementation of the Viterbi algorithm can be applied to the MAP algorithm. Bounds are derived for the dynamic range of the state metrics which enable the designer to optimize the word length. The computational kernel of the algorithm is the Add-MAX operation, which is the Add-Compare-Select operation of the Viterbi algorithm with an added offset. We show that the critical path of the algorithm can be reduced if the Add-MAX operation is reordered into an Offset-Add-Compare-Select operation by adjusting the location of registers. A general scheduling for the MAP algorithm is presented which gives the tradeoffs between computational complexity, latency, and memory size. Some of these architectures eliminate the need for RAM blocks with unusual form factors or can replace the RAM with registers. These architectures are suited to VLSI implementation of turbo decoders.

This paper surveys circuit innovations in ferroelectric memo

The speed at which two remote parties can exchange secret keys in continuous-variable quantum key distribution (CV-QKD) is currently limited by the computational complexity of key reconciliation. Multi-dimensional reconciliation using multi-edge lowdensity parity-check (LDPC) codes with low code rates and long block lengths has been shown to improve error-correction performance and extend the maximum reconciliation distance. We introduce a quasi-cyclic code construction for multi-edge codes that is highly suitable for hardware-accelerated decoding on a graphics processing unit (GPU). When combined with an 8dimensional reconciliation scheme, our LDPC decoder achieves an information throughput of 7.16 Kbit/s on a single NVIDIA GeForce GTX 1080 GPU, at a maximum distance of 142 km with a secret key rate of 6.64 × 10 −8 bits/pulse for a rate 0.02 code with block length of 10 6 bits. The LDPC codes presented in this work can be used to extend the previous maximum CV-QKD distance of 100 km to 142 km, while delivering up to 3.50× higher information throughput over the tight upper bound on secret key rate for a lossy channel.

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Delivering milliwatts of wireless power at centimeter distances is advantageous to many existing and emerging biomedical applications. It is highly desirable to fully integrate the receiver on a single chip in standard CMOS with no additional post-processing steps or external components. This paper presents a 2 × 2.18 mm(2) on-chip wireless power transfer (WPT) receiver (Rx) coil fabricated in 0.13 μm CMOS. The WPT system utilizes a 14.5 × 14.5 mm(2) transmitter (Tx) coil that is fabricated on a standard FR4 substrate. The on-chip power harvester demonstrates a peak WPT efficiency of -18.47 dB , -20.96 dB and -20.15 dB at 10 mm of separation through air, bovine muscle and 0.2 molar NaCl, respectively. The achieved efficiency enables the delivery of milliwatts of power to application circuits while staying below safe power density and electromagnetic (EM) exposure limits.