Wireless power transfer is commonly realized by means of near-field inductive coupling and is critical to many existing and emerging applications in biomedical engineering. This paper presents a closed form analytical solution for the optimum load that achieves the maximum possible power efficiency under arbitrary input impedance conditions based on the general two-port parameters of the network. The two-port approach allows one to predict the power transfer efficiency at any frequency, any type of coil geometry and through any type of media surrounding the coils. Moreover, the results are applicable to any form of passive power transfer such as provided by inductive or capacitive coupling. Our results generalize several well-known special cases. The formulation allows the design of an optimized wireless power transfer link through biological media using readily available EM simulation software. The proposed method effectively decouples the design of the inductive coupling two-port from the problem of loading and power amplifier design. Several case studies are provided for typical applications.

Delivering milliwatts of wireless power at centimeter distances is advantageous to many existing and emerging biomedical applications. It is highly desirable to fully integrate the receiver on a single chip in standard CMOS with no additional post-processing steps or external components. This paper presents a 2 × 2.18 mm(2) on-chip wireless power transfer (WPT) receiver (Rx) coil fabricated in 0.13 μm CMOS. The WPT system utilizes a 14.5 × 14.5 mm(2) transmitter (Tx) coil that is fabricated on a standard FR4 substrate. The on-chip power harvester demonstrates a peak WPT efficiency of -18.47 dB , -20.96 dB and -20.15 dB at 10 mm of separation through air, bovine muscle and 0.2 molar NaCl, respectively. The achieved efficiency enables the delivery of milliwatts of power to application circuits while staying below safe power density and electromagnetic (EM) exposure limits.

In this paper, a receiver front-end tailored to Bluetooth Low Energy applications is presented. In the proposed solution, the LNA, mixers, VCO, quadrature scheme and the first stage of the analog base-band share the same bias current under a 0.8 V voltage supply leading to a sub-mW power consumption. A channel selection filter, implemented through a current re-use gm-C topology, completes the design. The presented prototype, realized in 130 nm CMOS technology, occupies an active area of 0.25 mm while consuming only 0.6 mW. With a NF of 15.8 dB, an IIP3 of 17 dBm at the maximum gain and an image rejection above 30 dB the receiver front-end meets BLE noise figure, image rejection, phase noise and linearity requirements.

Pseudo-NMOS level-shifters consume large static current making them unsuitable for portable devices implemented with HV CMOS. Dynamic level-shifters help reduce power consumption. To reduce on-current to a minimum (subnanoamp), modifications are proposed to existing pseudo-NMOS and dynamic level-shifter circuits. A low power three transistor static level-shifter design with a resistive load is also presented.

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One of the main goals for the next generation of radios for wireless sensor and body-area networks (WSN and WBAN) is a sub-mW receiver (RX) compliant with energy-harvested supplies. In this direction, the Bluetooth standard has introduced a low-energy operative mode (BLE) with wider channel spacing (2MHz) and relaxed blocker tolerance. The minimum sensitivity required is -70dBm but even with a sensitivity 10dB lower the BLE receiver can have a noise figure close to 19dB [1]. Although linearity and noise specs have been significantly relaxed, the design of a sub-mW solution remains challenging since the power dissipation cannot be simply scaled with the spurious-freedynamic-range (SFDR). In fact, the ultimate bound is set by the power burned in the voltage-controlled oscillator (VCO), which is used for the generation of the local oscillator (LO) necessary for the signal downconversion. Since, for a targeted phase noise, the current required by the VCO is inversely proportional to the quality factor of the resonator adopted, a straightforward approach is to use a high-Q tank like the FBAR used by Wang et al. [2]. However in low-cost CMOS processes, when high-Q resonators are not present, an alternative strategy is to share the VCO bias current with the other blocks of the RF front-end as in the LMV cell proposed by Tedeschi et al. [3].

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