In this paper, a receiver front-end tailored to Bluetooth Low Energy applications is presented. In the proposed solution, the LNA, mixers, VCO, quadrature scheme and the first stage of the analog base-band share the same bias current under a 0.8 V voltage supply leading to a sub-mW power consumption. A channel selection filter, implemented through a current re-use gm-C topology, completes the design. The presented prototype, realized in 130 nm CMOS technology, occupies an active area of 0.25 mm while consuming only 0.6 mW. With a NF of 15.8 dB, an IIP3 of 17 dBm at the maximum gain and an image rejection above 30 dB the receiver front-end meets BLE noise figure, image rejection, phase noise and linearity requirements.
Floating point operations are important and essential part of many scientific and engineering applications. Floating point coprocessor (FPU) performs operations like addition, subtraction, division, square root, multiplication, fused multiply and accumulate and compare. Floating point operations are part of ARM, MIPS, and RISC-V etc. instruction sets. The FPU can be a part of hardware or be implemented in software. This paper details an architectural exploration for floating point coprocessor enabled with RISC-V [1] floating point instructions. The Floating unit that has been designed with RISC-V floating point instructions is fully compatible with IEEE 754-2008 standard as well. The floating point coprocessor is capable of handling both single and double precision floating point data operands in out-of-order for execution and in-order commit. The front end of the floating point processor accepts three data operands, rounding mode and associated Opcode fields for decoding. Each floating point operation is tagged with an instruction token for in-order completion and commit. The output of the floating point unit is tagged with either single or double precision results along with floating point exceptions, if any, based on the RISC-V instruction set. The coprocessor for floating point integrates with integer pipeline. The proposed architecture for floating point coprocessor with out-of-order execution, in-order commit and completion/retire has been synthesized, tested and verified on Xilinx Virtex 6 xc6vlx550t-2ff1759 FPGA. A system frequency of 240MHz for single precision floating point and 180 MHz double precision floating point operations has been observed on FPGA. Index Terms-IEEE 754 floating point standard, floating point co-processor, RISC processor, RISC-V instruction set, Microprocessor.
One of the main goals for the next generation of radios for wireless sensor and body-area networks (WSN and WBAN) is a sub-mW receiver (RX) compliant with energy-harvested supplies. In this direction, the Bluetooth standard has introduced a low-energy operative mode (BLE) with wider channel spacing (2MHz) and relaxed blocker tolerance. The minimum sensitivity required is -70dBm but even with a sensitivity 10dB lower the BLE receiver can have a noise figure close to 19dB [1]. Although linearity and noise specs have been significantly relaxed, the design of a sub-mW solution remains challenging since the power dissipation cannot be simply scaled with the spurious-freedynamic-range (SFDR). In fact, the ultimate bound is set by the power burned in the voltage-controlled oscillator (VCO), which is used for the generation of the local oscillator (LO) necessary for the signal downconversion. Since, for a targeted phase noise, the current required by the VCO is inversely proportional to the quality factor of the resonator adopted, a straightforward approach is to use a high-Q tank like the FBAR used by Wang et al. [2]. However in low-cost CMOS processes, when high-Q resonators are not present, an alternative strategy is to share the VCO bias current with the other blocks of the RF front-end as in the LMV cell proposed by Tedeschi et al. [3].
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