Review of recent shared memory based ATM switches

Sharma, Neeraj Kumar

doi:10.1016/s0140-3664(98)00266-7

Cited by 21 publications

(2 citation statements)

References 78 publications

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“…There has been much interest by the industrial and research communities in devising ATM switches capable of accommodating a variety of traffic sources with conflicting quality of service requirements. The combined use of techniques such as shared buffering and channel grouping in ATM switches has shown great benefits in terms of both performance and implementation [1][2][3][4]. Shared-buffer switches are known to have better performance and better utilization than input or output queued switches.…”

Section: Introductionmentioning

confidence: 99%

An approximate analysis of shared‐buffer channel‐grouped ATM switches under imbalanced traffic

Dang

Abonamah

2005

Int J Communication

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SUMMARYGrouping output channels in a shared-buffer ATM switch has shown to provide great saving in buffer space and better throughput under uniform traffic. However, uniform traffic does not represent a realistic view of traffic patterns in real systems. In this paper, we extend the queuing analysis of shared-buffer channel-grouped (SBCG) ATM switches under imbalanced traffic, as it better represent real-life situations. The study focuses on the impact of the grouping factor and other key switch design parameters on the performance of such switches as compared to the unichannel allocation scheme in terms of cell loss probability, throughput, mean cell delay and buffer occupancy. Numerical results from both the analytical model and simulation are presented, and the accuracy of the analysis is presented.

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Section: Introductionmentioning

confidence: 99%

An approximate analysis of shared‐buffer channel‐grouped ATM switches under imbalanced traffic

Dang

Abonamah

2005

Int J Communication

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“…Because SRAMs do not exist for N>2 at high speeds, another way of constructing the shared memory is required [6,7]. Two common approaches are the use of very wide memory or shared multi-buffer memories as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Optimized architecture and design of an output-queued CMOS switch chip

Luijten

Audigier²,

Gusat³

et al.

Proceedings Tenth International Conference on Computer Communications and Networks (Cat. No.01EX495)

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Traditional improvements in packet switch architecture aimed at increasing switch performance in terms of utilization, fairness and QoS. This paper focuses on improving architecture to achieve implementation feasibility of terabit aggregate data rates while maintaining such performance.Terabit class shared-memory switch chips are simple in concept but are a challenge to build due to the memory speed requirements and the complexity of wiring needed to connect these memories. Using a property of the combined shared memory and virtual output queuing switch architecture and a property of SRAMs, a new architecture is derived that enables construction of a terabit class switch fabric.

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