A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture

Kondoh, H.; Notani, H.; Yamanaka, Hidetoshi; Higashitani, K.; Saitō, Hideo; Hayashi, I.; Kohama, S.; Matsuda, Yoshihisa; Oshima, Koichiro; Nakaya, M.

doi:10.1109/4.222180

Cited by 23 publications

(8 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This corresponds to an architecture model factor of S = 4. The RAMs used in the Mitsubishi design have a minimum cycle time of 38.6 ns [6]. Considering the link rates and internal structure, the model indicates that the same performance could be achieved with buffer cycle times of 45 ns.…”

Section: L/nk Speedmentioning

confidence: 92%

“…Also plotted on the model curves of Fig. 2 are points corresponding to the AT&T 2.5 Gbis shared buffer switch [5] and the Mitsubishi 622 Mbis shared multibuffer switch [6]. The AT&T switch uses internal datapaths that are a full ATM cell in width (W = 424) and forms queues of waiting packets for its eight ports in a shared buffer area.…”

Section: E Figure 2 Model Curves For Electronic Atmswitchesmentioning

confidence: 99%

See 1 more Smart Citation

On the limits of electronic ATM switching

Butner¹,

Chivukula²

1996

IEEE Network

View full text Add to dashboard Cite

This article discusses the principal advantages and limitations of electronic switching in asynchronous transfer mode (ATM) networks. Key design parameters of ATM switch implementations are defined, and their relationships with respect to performance, complexity, and cost are modeled and discussed. Recent design and imple mentation experience is reported on a very hi h-performance four-in ut, four-outputLightning" project at the Universi of California, Santa Barbara. This research protronic switches operating at 40 Gg/s per link (TDM), with potential scalability to 100 Gb/s. Such aggressive link rates are near the implementation limits for electronic ATM switches; they place severe requirements on switch architecture, particularly the buffering scheme.

show abstract

Section: L/nk Speedmentioning

confidence: 92%

Section: E Figure 2 Model Curves For Electronic Atmswitchesmentioning

confidence: 99%

On the limits of electronic ATM switching

Butner¹,

Chivukula²

1996

IEEE Network

View full text Add to dashboard Cite

show abstract

“…During the same time slot cells are read from the memory modules and routed to their destination output ports through the output stage. In [8] an 8 x 8 switch is implemented using two 8 x 8 crossbars for the input and output stages. Unfortunately, the complexity of the crossbars limits the port scalability of this architecture.…”

Section: Multiple Shared Memory Switchmentioning

confidence: 99%

“…This limits the port scalability of such an architecture. To alleviate this problem several shared multibuffer architectures have been proposed [8], [l] [2]. A shared multibuffer switch consists of an input stage, a set of shared memory modules and an output stage.…”

Section: Multiple Shared Memory Switchmentioning

confidence: 99%

A multiple shared memory switch

Naraghi-Pour

Hegde

Reddy

Proceedings of 28th Southeastern Symposium on System Theory

View full text Add to dashboard Cite

One of the problems that shared memory switche,s have is that in order to build large switches the memory access requirements become stringent. One way to overcome this is to utilize multiple buflers which space division multiplex the input lines and thereby alleviate the memory access requirements. However, previous attempts to implement multibuffered shared memory switches have suffered from serious limitations. We describe in this work a multibuffered architecture that oflers tremendous potential. It is able to fully share the buffer, it guarantees the minimum delay switching of all cells, it can accomplish multicast and multi-channel switching, it can accommodate various priorities and classes of trafic while maintaining high performance o n account of very eficient buffer utilization.

show abstract

“…It is now almost unanimously agreed that ATM will become an enabling technology for the future integrated digital networks and thus nearly all large computer and communication companies have invested in developing ATM products [2,3,4,5]. However, most existing ATM products have been developed without attention to a fundamental problem of the ATM: trac control to maintain a satisfactory network performance.…”

mentioning

confidence: 99%

An enhanced timed-round-robin traffic control scheme for ATM networks

Qin

Proceedings of LCN - 21st Annual Conference on Local Computer Networks

View full text Add to dashboard Cite

ATM (asynchronous transfer mode) aims at providing both guaranteed bandwidth to support real-time communications and dynamic bandwidth sharing to accommodate bursty data traffic. Achievement of this goal is vital to make ATM an enabling technology for the future integrated digital networks. To realize this objective, good algorithms for controlling network traffic are required. This paper proposes a traffic control scheme which uses a timed-round-robin cell transmission scheduling algorithm enhanced with a simple feedback flow control mechanism to realize the promised advantages of ATM networks. Specifically, with the proposed scheme, a network is able to provide each user with (1) a guaranteed bandwidth, (2) immediate access to the full link bandwidth when there is no contention from other users, and (3) free of cell losses. An ATM switch design is also presented which shows the feasibility of implementing the proposed scheme with todayś switch architectures without adding much extra cost.This work may not be copied or reproduced in whole or in part for any commercial purpose. Permission to copy in whole or in part without payment of fee is granted for nonprofit educational and research purposes provided that all such whole or partial copies include the following: a notice that such copying is by permission of Mitsubishi Electric Research Laboratories, Inc.; an acknowledgment of the authors and individual contributions to the work; and all applicable portions of the copyright notice. Copying, reproduction, or republishing for any other purpose shall require a license with payment of fee to Mitsubishi Electric Research Laboratories, Inc. All rights reserved. Abstract ATM (asynchronous transfer mode) aims at providing both guaranteed bandwidth to support real-time communications and dynamic bandwidth sharing to accommodate bursty data trac. Achievement of this goal is vital to make ATM an enabling technology for the future integrated digital networks. To realize this objective, good algorithms for controlling network trac are required. This paper proposes a trac control scheme which uses a timed-round-robin cell transmission scheduling algorithm enhanced with a simple feedback ow control mechanism to realize the promised advantages of ATM networks. Specically, with the proposed scheme, a network is able to provide each user with (1) a guaranteed bandwidth, (2) immediate access to the full link bandwidth when there is no contention from other users, and (3) free of cell losses. An ATM switch design is also presented which shows the feasibility of implementing the proposed scheme with today's switch architectures without adding much extra cost.

show abstract

A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture

Cited by 23 publications

References 11 publications

On the limits of electronic ATM switching

On the limits of electronic ATM switching

A multiple shared memory switch

An enhanced timed-round-robin traffic control scheme for ATM networks

Contact Info

Product

Resources

About