This paper describes the design, fabrication, installation and performance of the new inner layer called Layer 0 (L0) that was inserted in the existing Run IIa Silicon MicroStrip Tracker (SMT) of the D0 experiment at the Fermilab Tevatron p p collider. L0 provides tracking information from two layers of sensors, which are mounted with center lines at a radial distance of 16.1 mm and 17.6 mm respectively from the beam axis. The sensors and readout electronics are mounted on a specially designed and fabricated carbon fiber structure that includes cooling for sensor and readout electronics. The structure has a thin polyimide circuit bonded to it so that the circuit couples electrically to the carbon fiber allowing the support structure to be used both for detector grounding and a low impedance connection between the remotely mounted hybrids and the sensors.

A digital focal plane array (DFPA) architecture has been developed that incorporates per-pixel full-dynamic-range analog-to-digital conversion and orthogonal-transfer-based realtime digital signal processing capability. Several long-wave infrared-optimized pixel processing focal plane readout integrated circuit (ROIC) designs have been implemented, each accommodating a 256 × 256 30-μm-pitch detector array. Demonstrated in this paper is the application of this DFPA ROIC architecture to problems of background pedestal mitigation, wide-field imaging, image stabilization, edge detection, and velocimetry. The DFPA architecture is reviewed, and pixel performance metrics are discussed in the context of the application examples. The measured data reported here are for DFPA ROICs implemented in 90-nm CMOS technology and hybridized to Hg x Cd 1−x Te (MCT) detector arrays with cutoff wavelengths ranging from 7 to 14.5 μm and a specified operating temperature of 60 K-80 K.

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