A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video

Kuo, Huang-Chih; Wu, Li-Cian; Huang, Hao-Ting; Hsu, Sheng-Yu; Lin, Youn-Long

doi:10.1109/tvlsi.2010.2045402

Cited by 26 publications

(16 citation statements)

References 8 publications

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“…The comparison shows that the proposed intra predictor is slightly larger than some other designs [2][3][4]. However, the proposed supports both the Plane mode and intra 8×8 whereas other designs support only one [3,[5][6][7] or neither of them [2,4]. Moreover, the proposed architecture supports all chroma formats and multi-QP coding for 4×4 and 8×8 modes.…”

Section: Implementation Results and Conclusionmentioning

confidence: 96%

“…Accumulated values H and V are multiplied by 5 by adding shifted values according to Eqs. (6) and (7). If a subsampled chroma is processed in a given dimension, the accumulated value is multiplied by 34 (the equations are modified according to the H.264/AVC specification).…”

Section: Plane Parameter Generatormentioning

confidence: 99%

“…In literature, there are some architectures of the H.264/AVC encoder intra prediction [2][3][4][5][6][7][8][9][10][11][12][13][14]. However, none of them supports all intra prediction modes available in High Profile.…”

Section: Introductionmentioning

confidence: 99%

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Intra Prediction for the Hardware H.264/AVC High Profile Encoder

Roszkowski

Pastuszak

2013

J Sign Process Syst

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The hardware implementation of the intra prediction described in this paper allows the H.264/AVC encoder to achieve optimal compression efficiency in real-time conditions. The architecture has some features that distinguish it from other solutions described in literature. Firstly, the architecture supports all intra prediction modes defined in High Profile of the H.264/AVC standard for all chroma formats. Secondly, the architecture can generate predictions for several quantization parameters. Thirdly, the hardware cost is reduced as the same resources are used to compute prediction samples for all the modes. Fourthly, the high sample-generation rate enables the encoder to achieve high throughputs. Fifthly, 4×4 block reordering and interleaving with other modes minimize the impact of the long-delay reconstruction loop on the encoder throughput. The architecture is verified against the JM.12 reference model and within the real-time FPGA hardware encoder. The synthesis results show that the design can operate at 100 MHz and 200 MHz for FPGA Aria II and 0.13 μm TSMC technology, respectively. These frequencies allow the encoder to support 720p and 1080p video at 30 fps.

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Section: Implementation Results and Conclusionmentioning

confidence: 96%

Section: Plane Parameter Generatormentioning

confidence: 99%

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Intra Prediction for the Hardware H.264/AVC High Profile Encoder

Roszkowski

Pastuszak

2013

J Sign Process Syst

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“…Similar to reusing hardware in HT/DCT and IHT/IDCT, we propose to combine the qunatizers and inverse quantizers in DC and AC paths. The Q and IQ use multipliers and barrel shifters for implementing their operations [10]. Since the goal is to reuse hardware for maximum area efficiency, the multipliers and barrel shifters are shared by interlacing Q and IQ.…”

Section: B Transform and Quantization Stagementioning

confidence: 99%

Multicast FullHD H.264 Intra Video Encoder Architecture

Khan

Shafique

Bauer

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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High throughput demands have resulted in enormous increase in complexity of multicast video applications, which require multiple video encoders to simultaneously compress individual views. In this work, we present an approach to encode independent videos using H.264 Intra encoder on a single hardware platform, where the hardware resources are shared by independent encoders in a time-multiplexed manner. In addition to lower the latency introduced by multicasting, we address the strong sequential data dependencies within the encoder. A 25 fps, 150 MHz prototype of the proposed encoder and multiple video capture/display on a mid-range FPGA is also presented.Index Terms Multicast, hardware sharing, H.264 encoder, FPGA implementation, FullHD video encoder.

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“…While the primary assumption of such techniques was to keep 100% correctness of the circuit functionality, later proposals [5], [6] exploited the error resiliency within the logic paths of the video codec circuits to push the voltage levels below the reliable operating points imposed by variabilities and imperfections in the fabrication process of sub 100 nanometer technologies. Some other approaches shown to be effective in power reduction of video codec applications are clock gating [7], [9], pipelining, use of unit level parallelism and multicore [8], [15].…”

Section: Introductionmentioning

confidence: 99%

Process variation aware transcoding for low power H.264 decoding

Amiri

Khajeh

Eltawil

et al. 2010

2010 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia

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Transcoding is commonly used in media servers to adapt video bitstreams to capabilities and specifications of the receiving playback devices or the transmission network channel in between. Primary adjustments are done on the video format, the resolution and the bitrate. In this paper we propose utilizing transcoding as a means of converting a regular standard video bitstream to a standard video bitstream that is also aware of power-reliability characteristics of the target decoder device with main focus on process variabilites within the on-chip decoder reference buffer memory. More specifically we introduce an H.264 video transcoding scheme in which the bitstream generated by transcoder is tolerant to defective SRAM cells that reside in the decoder reference buffer. Such error aware scheme allows for voltage scaling on decoder reference buffer in the presence of process variation and can result in significant power reduction considering the increasing power share of memories on SoCs. Our estimate shows this scheme can manage to realize about 40% power saving on decoder devices (in 32 nm) while preserving the decoded video quality and the bitrate of the bitstream.

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A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video

Cited by 26 publications

References 8 publications

Intra Prediction for the Hardware H.264/AVC High Profile Encoder

Intra Prediction for the Hardware H.264/AVC High Profile Encoder

Multicast FullHD H.264 Intra Video Encoder Architecture

Process variation aware transcoding for low power H.264 decoding

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