Multicast FullHD H.264 Intra Video Encoder Architecture

Abstract

High throughput demands have resulted in enormous increase in complexity of multicast video applications, which require multiple video encoders to simultaneously compress individual views. In this work, we present an approach to encode independent videos using H.264 Intra encoder on a single hardware platform, where the hardware resources are shared by independent encoders in a time-multiplexed manner. In addition to lower the latency introduced by multicasting, we address the strong sequential data dependencies within the encoder. A 25 fps, 150 MHz prototype of the proposed encoder and multiple video capture/display on a mid-range FPGA is also presented.Index Terms Multicast, hardware sharing, H.264 encoder, FPGA implementation, FullHD video encoder.

Hardware Efficient Integer Discrete Cosine Transform for Efficient Image/Video Compression

“…According to (9), if any v r,m has exactly the same norm as v r,0 , NV_R(v r,m ) will be 0 which means that v r,m does not encounter any norm variance. The same applies for NV_C(v c,n ) in (10). The average Norm Variance of the entire matrix d, which is denoted as NV A (d), can be computed as…”

“…H.264/Advanced Video Coding (AVC) [9], [10], Audio and Video Streaming (AVS) [11], Video Codec 1 (VC-1) [12], and high efficiency video coding (HEVC) [13], which uses 4-point to 32-point Int-DCT.…”