A low-impedance open-bitline array for multigigabit DRAM

Sekiguchi, Tomoko; Itoh, K.; Takahashi, Tsuyoshi; Sugaya, Masakazu; Fujisawa, Hironori; Nakamura, M.; Kajigaya, K.; Kimura, K.

doi:10.1109/4.991387

Cited by 32 publications

(10 citation statements)

References 12 publications

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“…None of these works show the impact of bitline coupling on retention time. In addition, [30] and [2] studied only DRAMs with a folded bitline architecture, while modern DRAMs use an open bitline architecture [22,24,32,33]. Open bitline architectures permit the use of smaller DRAM cells, improving DRAM density, but suffer from increased bitline-bitline coupling noise [33].…”

Section: Data Pattern Dependencementioning

confidence: 99%

“…Bitline-bitline coupling. Electrical coupling between adjacent bitlines creates noise on each bitline that depends on the voltages of nearby bitlines, such that the noise experienced by each bitline is affected by the values stored in nearby cells [26,33].…”

Section: Dram Retention Time Profilingmentioning

confidence: 99%

“…Electrical coupling between each bitline and wordline creates data-dependent noise on each wordline, which in turn creates data-dependent noise in each coupled bitline. Hence, the noise experienced by each bitline is affected by the values stored in every other cell in the row [20,33].…”

Section: Dram Retention Time Profilingmentioning

confidence: 99%

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An experimental study of data retention behavior in modern DRAM devices

LiuJamie

JaiyenBen

KimYoongu

et al. 2013

SIGARCH Comput. Archit. News

176

403

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DRAM cells store data in the form of charge on a capacitor. This charge leaks off over time, eventually causing data to be lost. To prevent this data loss from occurring, DRAM cells must be periodically refreshed. Unfortunately, DRAM refresh operations waste energy and also degrade system performance by interfering with memory requests. These problems are expected to worsen as DRAM density increases.The amount of time that a DRAM cell can safely retain data without being refreshed is called the cell's retention time. In current systems, all DRAM cells are refreshed at the rate required to guarantee the integrity of the cell with the shortest retention time, resulting in unnecessary refreshes for cells with longer retention times. Prior work has proposed to reduce unnecessary refreshes by exploiting differences in retention time among DRAM cells; however, such mechanisms require knowledge of each cell's retention time.In this paper, we present a comprehensive quantitative study of retention behavior in modern DRAMs. Using a temperaturecontrolled FPGA-based testing platform, we collect retention time information from 248 commodity DDR3 DRAM chips from five major DRAM vendors. We observe two significant phenomena: data pattern dependence, where the retention time of each DRAM cell is significantly affected by the data stored in other DRAM cells, and variable retention time, where the retention time of some DRAM cells changes unpredictably over time. We discuss possible physical explanations for these phenomena, how their magnitude may be affected by DRAM technology scaling, and their ramifications for DRAM retention time profiling mechanisms.

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Section: Data Pattern Dependencementioning

confidence: 99%

Section: Dram Retention Time Profilingmentioning

confidence: 99%

See 1 more Smart Citation

An experimental study of data retention behavior in modern DRAM devices

LiuJamie

JaiyenBen

KimYoongu

et al. 2013

SIGARCH Comput. Archit. News

176

403

View full text Add to dashboard Cite

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“…The two dimensional contour plot illustrates the sensitivity of data retention time versus a wide range of negative wordline voltages and cell capacitances, allowing us to determine the optimal targets for cell capacitance and negative wordline voltage after factoring in the device variations. Open-bitline architecture is inherently more sensitive to bitline and wordline noises than the folded bitline architecture [7] because the paired data and reference bitlines are located on the different sides of SA. As a result they are sensitive to the differential-mode wordline noise as shown in Fig.…”

Section: Retention Time Simulationmentioning

confidence: 99%

Retention time optimization for eDRAM in 22nm tri-gate CMOS technology

Wang

Arslan

Bisnik

et al. 2013

2013 IEEE International Electron Devices Meeting

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A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology.By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield. IntroductionThe demand for high density and low power embedded memory continues to grow as it provides a power-conscious solution to address memory bandwidth challenge and continue the performance improvement of modern multi-core SoC. Embedding DRAM technology based on a high-performance logic process has the advantage of enabling high-performance DRAM operation in a high-performance SoC because of the high-performance transistor and interconnects offered in the advanced technology nodes [1][2][3][4][5]. It has been demonstrated that a logic based eDRAM technology can provide higher memory density than conventional SRAM while consuming lower power. The integration of DRAM process with high-performance CMOS logic process poses a substantial challenge to achieve high data retention time and high performance at the same time as the required device characteristics for eDRAM cell and high-performance logic are significantly different. In this paper, noise reduction circuit techniques and device-design co-optimization schemes are described to achieve over 100μs data retention time for a Gbit eDRAM while maintaining its high frequency operation target. eDRAM Technology eDRAM technology featuring low leakage tri-gate access transistor and three-dimensional (3D) metal-insulator-metal (MIM) stacked capacitor was integrated into a 22nm tri-gate CMOS SoC process [5-6]. Fig. 1 shows the top and tilted SEMs of the 0.029um 2 eDRAM cell after gate patterning. Capacitor-over-bitline (COB) architecture is employed to achieve higher than 13fF/cell capacitance by embedding the 3D MIM capacitor in Metal-2 through Metal-4 copper interconnects with ultra-low-k interlayer dielectric as shown in Fig. 2. The use of tri-gate transistor enables the sub-pico-ampere leakage for access transistor to achieve over 100μs data retention time at 95°C. Fig. 3 shows the measured I D -V GS characteristics of access transistor at 95°C. The storage node is biased at 1V while the bitline node is biased at 0V. To further reduce access transistor leakage, a negative wordline voltage or wordline underdrive is applied to achieve low leakage at the storage node for "1" data bit with balanced gate induced drain leakage (GIDL) and subthreshold leakages.While the wordline underdrive is used to optimize access transistor leakage, wordline overdrive above 1.5V is utilized during the memory access to provide the drive current needed for speed and allows the MIM capacitor fully charged to supply voltage under the worst case access transistor V T variation. Fig. 3 ID-VGS of access transistor at 95°C. VD = 1V and VS = 0VFig. 1 SEMs of 22nm eDRAM bitcell after gate patterningFig. 2 Capacitor-over-bitline (COB) arc...

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“…This leads to sensing noise in the BLSA, resulting in a sensing failure. There are several noise sources that contribute to this sensing failure, but the major noise source is the coupling capacitance between the BL and the wordline (WL) [4], which leads to a cell MAT array noise as shown by the data patterns. We develop a BLSA to compensate for this MAT sensing noise.…”

mentioning

confidence: 99%

A bitline sense amplifier for offset compensation

Lee¹,

Kyung²,

Won³

et al. 2010

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

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The industry has continuously demanded lower voltages and higher densities in DRAM chips [1]. To satisfy this need, it is desirable to use a low V CORE in the DRAM core, even though with such a low voltage it is difficult to sense the cell signal due to an insufficient sensing margin in high density DRAM [2][3]. When the bitline (BL) sense amp (BLSA) starts the sensing operation, all the BLs in the cell array go to the data transition stage. This leads to sensing noise in the BLSA, resulting in a sensing failure. There are several noise sources that contribute to this sensing failure, but the major noise source is the coupling capacitance between the BL and the wordline (WL) [4], which leads to a cell MAT array noise as shown by the data patterns. We develop a BLSA to compensate for this MAT sensing noise. In this experiment, we fabricate a 68nm DRAM chip that shows only a 15% amplitude of the total normal chip noise by eliminating 85% of original MAT sensing noise by using a new BLSA scheme. Fabricated DRAM chips operate in the condition of V CORE = 1.5V and V DD = 1.8V. Generally, a sensing margin problem occurs in BLSAs with a large threshold voltage mismatch. Because this kind of worst-case BLSA is rare, we focus only on the worst BLSA found with a probability of 10 -3 %. All the measured data is from the BLSAs of 10 -3 % probability, which we define as a sensing margin failure.Figure 24.4.1 (a) shows an illustration of the MAT sensing noise mechanism, which depends on the data pattern. During the early stage of the sensing operation, the transition of the background BL affects the potential of the WL in the MAT, which leads to noise in the target BL. If the sensing margin in the target BL is not sufficient due to noise, the BLSA sensing fails. This noise is minimized or maximized in the two representative kinds of data patterns, which are composed of (a) all 1 (high) data bits and (b) only 1 (high) data bits with the background data bits all 0 (low), as shown in Fig. 24.4.2. We call (a)-data pattern a solid-1 pattern and (b)-data pattern an island-1 pattern. Complementary to the data patterns of Fig. 24.4.2, there are also solid-0 and island-0 data patterns. Figure 24.4.3 illustrates (a) the conventional BLSA and (b) our BLSA.The main difference between our BLSA and the usual BLSA is in whether the driving signal is separated or not. The driving signals are named RTO and SB in a conventional BLSA. In the case of our BLSA, there are 4 driving signals, which are named RTO_T, RTO_B, SB_T, and SB_B. The principle of this BLSA is related to the power consumption during the BLSA operation. When sensing an island-0 pattern, which consists of mostly one type of data, i.e., background 1 data, most of the BLSAs operate by one of the T and B driving signal, for example, RTO_T, SB_T. This results in RTO_T and SB_T supplying most of the power, while RTO_B, SB_B provide a clean power source to a BLSA sensing 0 data. This is because there is a large amount of current flow only over the RTO_T and SB_T line, while there is n...

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A low-impedance open-bitline array for multigigabit DRAM

Cited by 32 publications

References 12 publications

An experimental study of data retention behavior in modern DRAM devices

An experimental study of data retention behavior in modern DRAM devices

Retention time optimization for eDRAM in 22nm tri-gate CMOS technology

A bitline sense amplifier for offset compensation

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