An experimental study of data retention behavior in modern DRAM devices

Abstract

DRAM cells store data in the form of charge on a capacitor. This charge leaks off over time, eventually causing data to be lost. To prevent this data loss from occurring, DRAM cells must be periodically refreshed. Unfortunately, DRAM refresh operations waste energy and also degrade system performance by interfering with memory requests. These problems are expected to worsen as DRAM density increases.The amount of time that a DRAM cell can safely retain data without being refreshed is called the cell's retention time. In current systems, all DRAM cells are refreshed at the rate required to guarantee the integrity of the cell with the shortest retention time, resulting in unnecessary refreshes for cells with longer retention times. Prior work has proposed to reduce unnecessary refreshes by exploiting differences in retention time among DRAM cells; however, such mechanisms require knowledge of each cell's retention time.In this paper, we present a comprehensive quantitative study of retention behavior in modern DRAMs. Using a temperaturecontrolled FPGA-based testing platform, we collect retention time information from 248 commodity DDR3 DRAM chips from five major DRAM vendors. We observe two significant phenomena: data pattern dependence, where the retention time of each DRAM cell is significantly affected by the data stored in other DRAM cells, and variable retention time, where the retention time of some DRAM cells changes unpredictably over time. We discuss possible physical explanations for these phenomena, how their magnitude may be affected by DRAM technology scaling, and their ramifications for DRAM retention time profiling mechanisms.

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

“…Although the retention time of every DRAM cell is required to be greater than the 64ms minimum, different cells have different retention times. In this context, the cells with the shortest retention times are referred to as weak cells [45]. Intuitively, it would appear that the weak cells are especially vulnerable to disturbance errors since they are already leakier than others.…”

“…We searched for a module's weak cells by neither accessing nor refreshing a module for a generous amount of time (10 seconds) after having populated it with either all '0's or all '1's. If a cell was corrupted during this procedure, we considered it to be a weak cell [45]. In total, we were able to identify 1M weak cells for each module (984K, 993K, and 1.22M), which is on par with the number of victim cells.…”

Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

“…Literature from industry such as IBM [13,17], Intel [34], Samsung [16], and Toshiba [11], and academic groups [6,21,31] have proposed and/or used T ret profiling schemes. However, recent work [20] has pointed out that T ret profiling has to deal with Data Pattern Dependence (DPD) and Variable Retention Time (VRT) effects. As suggested in [20] and [13], profiling in the presence of DPD can be best done by using a variety of manufacturer-provided test patterns -e.g., all 0s/1s, checkerboard, walk and random.…”

“…However, recent work [20] has pointed out that T ret profiling has to deal with Data Pattern Dependence (DPD) and Variable Retention Time (VRT) effects. As suggested in [20] and [13], profiling in the presence of DPD can be best done by using a variety of manufacturer-provided test patterns -e.g., all 0s/1s, checkerboard, walk and random. One of the papers [20] also points out that VRT changes are slow (in the order of hours and sometimes a day) and, therefore, one could profile periodically.…”

“…As suggested in [20] and [13], profiling in the presence of DPD can be best done by using a variety of manufacturer-provided test patterns -e.g., all 0s/1s, checkerboard, walk and random. One of the papers [20] also points out that VRT changes are slow (in the order of hours and sometimes a day) and, therefore, one could profile periodically. Note that a tile in Mosaic will include over 10,000 cells.…”