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Cointegration of multistate single-transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide semiconductor (CMOS) fabrication. The neurons and synapses were integrated on the same plane with the same process because they have the same structure of a metal-oxide semiconductor field-effect transistor with different functions such as homotype. By virtue of 100% CMOS compatibility, it was also realized to cointegrate the neurons and synapses with additional CMOS circuits. Such cointegration can enhance packing density, reduce chip cost, and simplify fabrication procedures. The multistate single-transistor neuron that can control neuronal inhibition and the firing threshold voltage was achieved for an energy-efficient and reliable neural network. Spatiotemporal neuronal functionalities are demonstrated with fabricated single-transistor neurons and synapses. Image processing for letter pattern recognition and face image recognition is performed using experimental-based neuromorphic simulation.

Most IoT products or their constituent elements such as chips are vulnerable to various types of security attack, such as side channel attacks and physical cloning attacks. [2][3][4] Stored or processed information can be exposed to a hacker via timing analysis, [5] power analysis, [6] electromagnetic radiation analysis, [7] data remanence analysis, [8] etc.There are several kinds of security methods, such as embedded security element, [9] trusted platform module, [10] and true random number generator, [11,12] have been proposed to improve security and save power consumption of IoT devices. Alternatively, a physical unclonable function (PUF) device has also attracted considerable attention to address the aforementioned shortcomings. [13][14][15][16] The PUF should be unpredictable, irreproducible, and statistically unbiased, based on inherent randomness derived from the unavoidable variability that occurs during device fabrication. A PUF in a chip can be analogous to a fingerprint or an iris in a human. With these features, the PUF generates distinctive challenge/response pairs to allow security functions such as authentication and key storage. And it can also be used for anti-counterfeiting integrated circuits, protecting intellectual property, and software licensing. [17] To implement an ideal PUF, two essential conditions should be satisfied: 1) it must be easy to create randomness but impossible to predict it, and 2) it must be easy to make a PUF device but difficult to duplicate it.PUF devices can be categorized into roughly three groupscircuit-based PUF, memory-based PUF and the other types including micro-electro-mechanical-system (MEMS) PUF, and optical PUF. The circuit-based PUF such as arbiter PUF, [18] ring oscillator (RO) PUF, [19] and glitch PUF, [20] primarily used a delay time as a representative metric. The memorybased PUF, including static random access memory (SRAM) PUF, [21,22] flash memory PUF, [23,24] RRAM PUF, [25,26] DRAM PUF [27,28] used device-to-device variations arisen from microfabrication [29][30][31][32] as the typical variables. A few representatives are the variations of on-state current, threshold voltage, retention time, etc.With the advance of internet of things, numerous electronic devices are being connected to each other through the internet. As the number of connections has increased, security has become increasingly important. Physically unclonable function (PUF) is one of the essential approaches that can be used to secure data in device. In this work, an independently controlled double-gate (ICDG) transistor composed of a poly-crystalline silicon (poly-Si) nanowire channel for PUF is first demonstrated. Simply fabricated using CMOS processes, the so-called PUF transistor harnesses multi-states and self-destruction for advanced security. The randomness in the poly-Si nanowire channel is established by the randomly distributed poly-Si grains. This random distribution means each transistor has a different threshold voltage (V th ). Moreover, multi-states composed of a primar...

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A ternary logic decoder (TLD) is demonstrated with independently controlled double-gate (ICDG) silicon-nanowire (Si-NW) MOSFETs to confirm a feasibility of mixed radix system (MRS). The TLD is essential component for realization of the MRS. The ICDG Si-NW MOSFET resolves the limitations of the conventional multi-threshold voltage (multi-Vth) schemes required for the TLD. The ICDG Si-NW MOSFETs were fabricated and characterized. Afterwards, their electrical characteristics were modeled and fitted semi-empirically with the aid of SILVACO ATLAS TCAD simulator. The circuit performance and power consumption of the TLD were analyzed using ATLAS mixed-mode TCAD simulations. The TLD showed a power-delay product of 35 aJ for a gate length (LG) of 500 nm and that of 0.16 aJ for LG of 14 nm. Thanks to its inherent CMOS-compatibility and scalability, the TLD based on the ICDG Si-NW MOSFETs would be a promising candidate for a MRS using ternary and binary logic.

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Although SRAM is a well established type of volatile memory, data remanence has been observed at low temperature even for a power-off state, and thus it is vulnerable to a physical cold boot attack. To address this, an ultra-fast data sanitization method within 5 ns is demonstrated with physics-based simulations for avoidance of the cold boot attack to SRAM. Back-bias, which can control device parameters of CMOS, such as threshold voltage and leakage current, was utilized for the ultra-fast data sanitization. It is applicable to temporary erasing with data recoverability against a low-level attack as well as permanent erasing with data irrecoverability against a high-level attack.