Cointegration of single-transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware

Abstract

Cointegration of multistate single-transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide semiconductor (CMOS) fabrication. The neurons and synapses were integrated on the same plane with the same process because they have the same structure of a metal-oxide semiconductor field-effect transistor with different functions such as homotype. By virtue of 100% CMOS compatibility, it was also realized to cointegrate the neurons and synapses with additional CMOS circuits. Such cointegration can enhance packing density, reduce chip cost, and simplify fabrication procedures. The multistate single-transistor neuron that can control neuronal inhibition and the firing threshold voltage was achieved for an energy-efficient and reliable neural network. Spatiotemporal neuronal functionalities are demonstrated with fabricated single-transistor neurons and synapses. Image processing for letter pattern recognition and face image recognition is performed using experimental-based neuromorphic simulation.

Self‐Powered Artificial Mechanoreceptor Based on Triboelectrification for a Neuromorphic Tactile System

“…A biristor neuron can mimic a neuronal integrate‐and‐fire (IF) function and spiking operation by means of the single‐transistor latch (STL) phenomenon. [ 30 , 31 , 32 ] In this work, a biristor neuron with a base width ( W B ) of 250 nm and a base length ( L B ) of 500 nm was fabricated, as shown in the scanning electron microscope (SEM) image in Figure 3 a . The fabrication details are provided in Figure S2 , Supporting Information.…”

“…It is worth noting that I in should be higher than the lower boundary of the forbidden region ( I limit ) marked in Figure 3b . [ 30 , 31 , 32 ] Unless I in is larger than I limit , charge integration cannot be enabled. This feature is similar to a biological neuron function where spiking is disabled when the input stimulus does not exceed a threshold value.…”

“…[ 25 , 26 , 27 , 28 , 29 ] The biristor neuron is considered a possible candidate to replace bulky and high‐energy‐consuming CMOS circuit‐based spiking neurons for SNNs. [ 30 , 31 , 32 ] After analyzing the characteristics of the TENG and the biristor neuron, a self‐powered artificial mechanoreceptor module capable of detection near 3 kPa that is able to sense a gentle touch such as, handwriting and breathing is realized by connecting the two abovementioned components. Based on the spiking characteristics according to the pressure, classification of handwritten digits in the Modified National Institute of Standards and Technology (MNIST) dataset is performed with the aid of a software simulation in order to demonstrate that complex pattern recognition is possible with the neuromorphic tactile system composed of an artificial mechanoreceptor module.…”

Periodicity Pitch Perception Part III: Sensibility and Pachinko Volatility

“…The stateful temporal logic algebra system is realizable as a neuromorphic circuit built with the seven building blocks FA , LA , D , C , M , I , R and is implementable for various hardware target architectures. It is especially suited for implementation in CMOS (Nair et al, 2020 ; Han et al, 2021 ), FPGA (Yang et al, 2021a ), and quantum-based hardware (Varadarajan, 2014 ; Gonzalez-Raya et al, 2019 ; Hamilton et al, 2019 ; Shi et al, 2019 ; Lamata, 2020 ; Marković et al, 2020 ) as nanobridge atomic switch FPGAs (Demis et al, 2015 ; Sharma et al, 2021 ) superconducting accelerators (Tzimpragos et al, 2020 ; Vakili et al, 2020 ; Feldhoff and Toepfer, 2021 ), superconducting nanowires (Toomey et al, 2019 ), nanowire networks (Diaz-Alvarez et al, 2020 ; Kendall et al, 2020 ; Kuncic et al, 2020 ; Li et al, 2020 ; Milano et al, 2020 ; Dunham et al, 2021 ; Kendall, 2021 ) and memristors (Sanz et al, 2018 ; Woźniak et al, 2020 ).…”

A Survey on Spiking Neural Networks

“…In the semiconductor sectors, there have been designed and experimentally fabricated the neuron models and synaptic connections using CMOS and Memristor Technologies [62]. They have just shown the possibility of energy-efficient neuromorphic chips.…”