Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

Abstract

EDRAM cells require periodic refresh, which ends up consuming substantial energy for large last-level caches. In practice, it is well known that different eDRAM cells can exhibit very different charge-retention properties. Unfortunately, current systems pessimistically assume worst-case retention times, and end up refreshing all the cells at a conservatively-high rate. In this paper, we propose an alternative approach. We use known facts about the factors that determine the retention properties of cells to build a new model of eDRAM retention times. The model is called Mosaic. The model shows that the retention times of cells in large eDRAM modules exhibit spatial correlation. Therefore, we logically divide the eDRAM module into regions or tiles, profile the retention properties of each tile, and program their refresh requirements in small counters in the cache controller. With this architecture, also called Mosaic, we refresh each tile at a different rate. The result is a 20x reduction in the number of refreshes in large eDRAM modules -practically eliminating refresh as a source of energy consumption.

A reuse-based refresh policy for energy-aware eDRAM caches

“…The refresh overhead problem in on-chip eDRAM caches has been previously addressed, taking into account inter-cell feature variations [12,9,13]. This prior work pursued solutions that are orthogonal to our proposed selective refresh.…”

“…A common approach to reduce this overhead is to lower the impact of inter-cell variability on refresh energy [12,9,13]. Other work has considered using time-based dead-block predictors [14] and cache block state [15] for filtering refresh requests.…”

“…The Mosaic [13] architecture minimizes the number of refresh operations required by exploiting the fact that cell retention times of eDRAM caches exhibit spatial correlation. The cache is divided into regions with different retention time requirements, and the contents of each region are refreshed at different rates using counters in the cache controller.…”

Extreme-scale computer architecture: Energy efficiency from the ground up

“…This approach relies on profiling the retention times of different on-chip eDRAM modules or regions. For example, one can exploit the spatial correlation of the retention times of the eDRAM cells [15]. With this technique and similar ones, we may refresh most of the eDRAM with long refresh periods, and only a few small sections with the conventional, short refresh periods.…”

“…However, eDRAM needs to be refreshed. Fortunately, refresh is done at the fine-grained level of a cache line, and we can design intelligent refresh schemes [14], [15].…”