A reuse-based refresh policy for energy-aware eDRAM caches

Valero, Alejandro; Petit, Salvador; Sahuquillo, Julio; Kaeli, David; Duato, J.

doi:10.1016/j.micpro.2014.12.001

Cited by 5 publications

(1 citation statement)

References 31 publications

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“…Understanding of such an impact is crucial for facilitating the co-design of software and hardware techniques to improve DRAM energy efficiency. Other research studies proposed various fine-grained schemes to reduce the number of refresh operations and thus improve DRAM energy efficiency [17], [21], [34], [73], [82], [86]. Although some of these studies utilize workload inherent features, such as the memory reuse time, they are orthogonal to our work.…”

Section: Related Workmentioning

confidence: 99%

Workload-Aware DRAM Error Prediction using Machine Learning

Mukhanov

Tovletoglou

Vandierendonck

et al. 2019

2019 IEEE International Symposium on Workload Characterization (IISWC)

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The aggressive scaling of technology may have helped to meet the growing demand for higher memory capacity and density, but has also made DRAM cells more prone to errors. Such a reality triggered a lot of interest in modeling DRAM behavior for either predicting the errors in advance or for adjusting DRAM circuit parameters to achieve a better tradeoff between energy efficiency and reliability. Existing modeling efforts may have studied the impact of few operating parameters and temperature on DRAM reliability using custom FPGAs setups, however they neglected the combined effect of workloadspecific features that can be systematically investigated only on a real system.In this paper, we present the results of our study on workloaddependent DRAM error behavior within a real server considering various operating parameters, such as the refresh rate, voltage and temperature. We show that the rate of single-and multi-bit errors may vary across workloads by 8x, indicating that program inherent features can affect DRAM reliability significantly. Based on this observation, we extract 249 features, such as the memory access rate, the rate of cache misses, the memory reuse time and data entropy, from various compute-intensive, caching and analytics benchmarks. We apply several supervised learning methods to construct the DRAM error behavior model for 72 servergrade DRAM chips using the memory operating parameters and extracted program inherent features. Our results show that, with an appropriate choice of program features and supervised learning method, the rate of single-and multi-bit errors can be predicted for a specific DRAM module with an average error of less than 10.5 %, as opposed to the 2.9x estimation error obtained for a conventional workload-unaware error model. Our model enables designers to predict DRAM errors in advance for less than a second and study the impact of any workload and applied software optimizations on DRAM reliability.

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