INTRODUCTIONAs the dynamic random-access memory (DRAM) design rule shrinks to gigabit scale, the gate Resistance-Capacitance (RC) delay is placing serious limitations on device performance. Employing polymetal to replace polycide (tungsten silicide/polysilicon) as a metal-oxide semiconductor field-effect transistor (MOSFET) gate material has been sought for years to reduce the resistivity. Among many other choices, the tungsten/diffusion barrier/polysilicon multilayered gate has widely been studied and developed because of its low resistivity, good thermal stability, and low diffusivity. 1-3 The main focus of the development has been on the formation of a diffusion barrier between tungsten and polysilicon, 1 the process compatibility with respect to the conventional polycide-gate process, 3,4 and the reliability and performance improvement of MOSFET devices. 2 In forming the tungsten-nitride diffusion barrier between tungsten and polysilicon, the "denudation" of the tungsten process has demonstrated even lower tungsten-electrode resistivity and simplified the deposition process over the usual twostep deposition of barrier and electrode. For the tungsten-denudation process, a mixture of tungsten and nitrogen is deposited. The diffusion barrier at the interface and the low resistivity tungsten electrode are formed in situ, upon applying the hightemperature denudation heat treatment because nitrogen atoms either segregate at the interface or diffuse out. The incompatibility of the polymetalgate process with respect to the polycide-gate process arises in the reoxidation for curing gate-etch damage and post-etch cleaning. The thermodynamic condition dictating selective oxidation that allows silicon only to oxidize is now well established. 1 Some new cleaning chemicals have also been developed to reduce the damage on tungsten. 4 Most of these process schemes have been confirmed on wafer-level direct-current (DC) parameters and have yet to be demonstrated on chip-level performance. We reported earlier 3 on the fully working, 256-megabit, DRAM devices employing the polymetal-gate process for the first time. The objective of this work is to describe in detail some of the This paper summarizes the problems and solutions in the process integration and device and circuit performances of fully working, 256-megabit, dynamic random-access memory (DRAM) chips employing poly-metal gate. In the circuit analysis, an anomalous decay of the electrical signal was observed as the signal proceeds through the delays. A circuit simulation suggested the presence of parasitic components in the gate tungsten/polysilicon interface. The experiments on the tungsten-electrode formation and metal-to-gate contact formation schemes confirmed the effects of the parasitic components when the scheme employing an in-situ formation of diffusion barrier is used. The search for a new cleaning chemical for the postgate etch process was also considered in the integration because it was found to significantly affect the data-retention characteristics. Finall...
The industry has continuously demanded lower voltages and higher densities in DRAM chips [1]. To satisfy this need, it is desirable to use a low V CORE in the DRAM core, even though with such a low voltage it is difficult to sense the cell signal due to an insufficient sensing margin in high density DRAM [2][3]. When the bitline (BL) sense amp (BLSA) starts the sensing operation, all the BLs in the cell array go to the data transition stage. This leads to sensing noise in the BLSA, resulting in a sensing failure. There are several noise sources that contribute to this sensing failure, but the major noise source is the coupling capacitance between the BL and the wordline (WL) [4], which leads to a cell MAT array noise as shown by the data patterns. We develop a BLSA to compensate for this MAT sensing noise. In this experiment, we fabricate a 68nm DRAM chip that shows only a 15% amplitude of the total normal chip noise by eliminating 85% of original MAT sensing noise by using a new BLSA scheme. Fabricated DRAM chips operate in the condition of V CORE = 1.5V and V DD = 1.8V. Generally, a sensing margin problem occurs in BLSAs with a large threshold voltage mismatch. Because this kind of worst-case BLSA is rare, we focus only on the worst BLSA found with a probability of 10 -3 %. All the measured data is from the BLSAs of 10 -3 % probability, which we define as a sensing margin failure.Figure 24.4.1 (a) shows an illustration of the MAT sensing noise mechanism, which depends on the data pattern. During the early stage of the sensing operation, the transition of the background BL affects the potential of the WL in the MAT, which leads to noise in the target BL. If the sensing margin in the target BL is not sufficient due to noise, the BLSA sensing fails. This noise is minimized or maximized in the two representative kinds of data patterns, which are composed of (a) all 1 (high) data bits and (b) only 1 (high) data bits with the background data bits all 0 (low), as shown in Fig. 24.4.2. We call (a)-data pattern a solid-1 pattern and (b)-data pattern an island-1 pattern. Complementary to the data patterns of Fig. 24.4.2, there are also solid-0 and island-0 data patterns. Figure 24.4.3 illustrates (a) the conventional BLSA and (b) our BLSA.The main difference between our BLSA and the usual BLSA is in whether the driving signal is separated or not. The driving signals are named RTO and SB in a conventional BLSA. In the case of our BLSA, there are 4 driving signals, which are named RTO_T, RTO_B, SB_T, and SB_B. The principle of this BLSA is related to the power consumption during the BLSA operation. When sensing an island-0 pattern, which consists of mostly one type of data, i.e., background 1 data, most of the BLSAs operate by one of the T and B driving signal, for example, RTO_T, SB_T. This results in RTO_T and SB_T supplying most of the power, while RTO_B, SB_B provide a clean power source to a BLSA sensing 0 data. This is because there is a large amount of current flow only over the RTO_T and SB_T line, while there is n...
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
customersupport@researchsolutions.com
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.