Process optimization of polymetal (W/WN/Polysilicon) gate and its impact on dynamic random-access memory chip performance in 0.14-µm technology

Abstract

INTRODUCTIONAs the dynamic random-access memory (DRAM) design rule shrinks to gigabit scale, the gate Resistance-Capacitance (RC) delay is placing serious limitations on device performance. Employing polymetal to replace polycide (tungsten silicide/polysilicon) as a metal-oxide semiconductor field-effect transistor (MOSFET) gate material has been sought for years to reduce the resistivity. Among many other choices, the tungsten/diffusion barrier/polysilicon multilayered gate has widely been studied and developed because of its low resistivity, good thermal stability, and low diffusivity. 1-3 The main focus of the development has been on the formation of a diffusion barrier between tungsten and polysilicon, 1 the process compatibility with respect to the conventional polycide-gate process, 3,4 and the reliability and performance improvement of MOSFET devices. 2 In forming the tungsten-nitride diffusion barrier between tungsten and polysilicon, the "denudation" of the tungsten process has demonstrated even lower tungsten-electrode resistivity and simplified the deposition process over the usual twostep deposition of barrier and electrode. For the tungsten-denudation process, a mixture of tungsten and nitrogen is deposited. The diffusion barrier at the interface and the low resistivity tungsten electrode are formed in situ, upon applying the hightemperature denudation heat treatment because nitrogen atoms either segregate at the interface or diffuse out. The incompatibility of the polymetalgate process with respect to the polycide-gate process arises in the reoxidation for curing gate-etch damage and post-etch cleaning. The thermodynamic condition dictating selective oxidation that allows silicon only to oxidize is now well established. 1 Some new cleaning chemicals have also been developed to reduce the damage on tungsten. 4 Most of these process schemes have been confirmed on wafer-level direct-current (DC) parameters and have yet to be demonstrated on chip-level performance. We reported earlier 3 on the fully working, 256-megabit, DRAM devices employing the polymetal-gate process for the first time. The objective of this work is to describe in detail some of the This paper summarizes the problems and solutions in the process integration and device and circuit performances of fully working, 256-megabit, dynamic random-access memory (DRAM) chips employing poly-metal gate. In the circuit analysis, an anomalous decay of the electrical signal was observed as the signal proceeds through the delays. A circuit simulation suggested the presence of parasitic components in the gate tungsten/polysilicon interface. The experiments on the tungsten-electrode formation and metal-to-gate contact formation schemes confirmed the effects of the parasitic components when the scheme employing an in-situ formation of diffusion barrier is used. The search for a new cleaning chemical for the postgate etch process was also considered in the integration because it was found to significantly affect the data-retention characteristics. Finall...

Study on the oxidation and reduction of tungsten surface for sub-50 nm patterning process

“…[7][8][9][10] Tungsten (W) has the most attention among various materials as the next-generation word line to replace silicon, due to advantage such as high thermal stability, sheet resistance lower than 5 X/sq, uniform resistance per area regardless of pattern size, and excellent patterning properties due to the small grain size. [11][12][13][14] Other properties required for nanoscale patterning regarding factors such as contamination, morphology, resistance control, surface reaction, and patterning properties have been considered. 11,15 However, the oxidation of tungsten surfaces during processing is a critical problem that needs to be solved for the application of tungsten as the word line for nanoscale semiconductor devices.…”