Low resistive tungsten dual poly-metal gates with multi-diffusion barrier metals in high performance memory devices

International audienceExchange bias based spintronics devices involve ferromagnetic/antiferromagnetic interfaces and concomitant layers intermixing. As a consequence, interfacial spin-glass-like phases with reduced properties and increased dispersions form and lower the device performance. It is therefore necessary to limit intermixing by introduction of diffusion barriers. One of the major difficulties is that the barrier must be inert. This paper uses blocking temperature distributions to quantify the interfacial quality of Co/IrMn based stacks. Inserting a (Cu/Pt) dual barrier fulfils the manifold requirements of limiting Co-Mn, Co-Pt, and Cu-Mn intermixing, which takes place when using either no or single Pt and Cu barriers, respectivel

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Low resistive tungsten dual poly-metal gates with multi-diffusion barrier metals in high performance memory devices

Cited by 2 publications

References 13 publications

Process engineering to reduce self-aligned contact failure by reducing process-driven thermal stress on tungsten-dual poly gate stacks in sub-60 nm DRAM devices

Process engineering to reduce self-aligned contact failure by reducing process-driven thermal stress on tungsten-dual poly gate stacks in sub-60 nm DRAM devices

Benefit of inserting a (Cu/Pt) intermixing dual barrier for the blocking temperature distribution of exchange biased Co/(Cu/Pt)/IrMn stacks

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