A bitline sense amplifier for offset compensation

Abstract

The industry has continuously demanded lower voltages and higher densities in DRAM chips [1]. To satisfy this need, it is desirable to use a low V CORE in the DRAM core, even though with such a low voltage it is difficult to sense the cell signal due to an insufficient sensing margin in high density DRAM [2][3]. When the bitline (BL) sense amp (BLSA) starts the sensing operation, all the BLs in the cell array go to the data transition stage. This leads to sensing noise in the BLSA, resulting in a sensing failure. There are several noise sources that contribute to this sensing failure, but the major noise source is the coupling capacitance between the BL and the wordline (WL) [4], which leads to a cell MAT array noise as shown by the data patterns. We develop a BLSA to compensate for this MAT sensing noise. In this experiment, we fabricate a 68nm DRAM chip that shows only a 15% amplitude of the total normal chip noise by eliminating 85% of original MAT sensing noise by using a new BLSA scheme. Fabricated DRAM chips operate in the condition of V CORE = 1.5V and V DD = 1.8V. Generally, a sensing margin problem occurs in BLSAs with a large threshold voltage mismatch. Because this kind of worst-case BLSA is rare, we focus only on the worst BLSA found with a probability of 10 -3 %. All the measured data is from the BLSAs of 10 -3 % probability, which we define as a sensing margin failure.Figure 24.4.1 (a) shows an illustration of the MAT sensing noise mechanism, which depends on the data pattern. During the early stage of the sensing operation, the transition of the background BL affects the potential of the WL in the MAT, which leads to noise in the target BL. If the sensing margin in the target BL is not sufficient due to noise, the BLSA sensing fails. This noise is minimized or maximized in the two representative kinds of data patterns, which are composed of (a) all 1 (high) data bits and (b) only 1 (high) data bits with the background data bits all 0 (low), as shown in Fig. 24.4.2. We call (a)-data pattern a solid-1 pattern and (b)-data pattern an island-1 pattern. Complementary to the data patterns of Fig. 24.4.2, there are also solid-0 and island-0 data patterns. Figure 24.4.3 illustrates (a) the conventional BLSA and (b) our BLSA.The main difference between our BLSA and the usual BLSA is in whether the driving signal is separated or not. The driving signals are named RTO and SB in a conventional BLSA. In the case of our BLSA, there are 4 driving signals, which are named RTO_T, RTO_B, SB_T, and SB_B. The principle of this BLSA is related to the power consumption during the BLSA operation. When sensing an island-0 pattern, which consists of mostly one type of data, i.e., background 1 data, most of the BLSAs operate by one of the T and B driving signal, for example, RTO_T, SB_T. This results in RTO_T and SB_T supplying most of the power, while RTO_B, SB_B provide a clean power source to a BLSA sensing 0 data. This is because there is a large amount of current flow only over the RTO_T and SB_T line, while there is n...

Selective negative word line scheme for improving refresh

“…Introduction: In the DRAM industry, the negative word line (NWL) scheme [1] is presently one of the most representative techniques used for low voltage operation [2][3][4]. However, it also has disadvantages, such as gate-induced drain leakage (GIDL) [5].…”