A highly stable reliable SRAM cell design for low power applications

Pal, Soumitra; Bose, Subhankar; Ki, Wing-Hung; Islam, Aminul

doi:10.1016/j.microrel.2019.113503

Cited by 42 publications

(12 citation statements)

References 42 publications

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“…Shorter T RA of the SEHF11T compared to the FD8T cell can be explained by the body‐source voltage ( V BS ) effect caused by read buffer in the cell and increase in the QB node voltage of FD8T during read operation 36 . Assuming Q / QB stores “0”/“1” during read operation, it is observed that the intermediate node voltage of X 2 in the SEHF11T goes up from zero to 112 mV and then gradually goes down to 107 mV at the time of recording of T RA .…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…The body bias acts as a tuning knob to reimburse for parameter variations 37 . Body biasing, contrarily, is more effective for fluctuations addressing in various design metrics because of process and temperature variations 36 . Therefore, from Figure 7B, which indicates the reliability of SRAM cells under PVT variations, it is observed a 1.17X, 1.11X, and 1.07X improvement in T RA distribution, in terms of T RA variability, in the SEHF11T compared to FD8T, HFBS9T, and SEDF9T at V DD = 0.7 V, respectively.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…The speed of write operation is indicated by write access time (write delay) T WA , which is defined as the time duration between the WL activation and the time when node Q / QB reaches to 10%/90% of V DD . 4 Since write “1” operation is worst case in the single‐ended cells, 36 we have plotted the T WA of writing “1” for all cells at different V DD values, as shown in Figure 10A. The FD8T and HFBS9T cells employ differential writing scheme; hence, T WA for these cells is shorter than other cells.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…Table 4 summarizes some cell features and main design metrics of the proposed SEHF11T cell compared to FD8T, 10 HFBS9T, 16 and SEDF9T 15 cells at V DD = 0.7 V. In addition to these cells, recently proposed SRAM cells such as the transmission gate‐based 9T (TG9T) cell, 2 the single‐ended write‐assist 10T (SEWA10T) cell, 36 the ultra‐low power data‐dependent power‐supplied 11T (D2P11T) cell, 38 the low power single‐ended 11T (LPSE11T) cell, 39 the data‐dependent PC 12T (D2PC12T) cell, 40 and the bit‐interleaving 12T (BI12T) cell 22 have been also considered. These cells with proper sizes are compared with the proposed SEHF11T cell at V DD = 0.7 V, for comprehensive comparison.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

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Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

Circuit Theory & Apps

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Summary This paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

Section: Simulation Results and Discussionmentioning

confidence: 99%

Section: Simulation Results and Discussionmentioning

confidence: 99%

Section: Simulation Results and Discussionmentioning

confidence: 99%

See 2 more Smart Citations

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

Circuit Theory & Apps

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“…Many SRAM bit-cell design [ 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 ] have been presented to enhance circuit stability for robust low voltage/power operation. In [ 9 , 10 , 11 , 12 , 13 , 14 , 15 ], are provided stacked transistors to solve the problem of half-selected read error, but they bring worse write capacity. In order to overcome this problem, a word line boost circuit technology to improve the write capability are presented in [ 16 , 17 ].…”

Section: Introductionmentioning

confidence: 99%

A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications

Sheu

Tsai

et al. 2021

Sensors

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An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ.

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Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

Pal

Divya

et al. 2021

Circuit Theory & Apps

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In advanced technology, static random-access memory (SRAM) cells used in space are highly sensitive to charge variations caused by high-energy particle strikes, which cause soft-error. Therefore, it is imperative for an SRAM to withstand this harsh environment. However, 6T cells are unable to function reliably in such a place. In order to address this, a radiation-hardened readdecoupled 12T (RHRD12T) SRAM cell is proposed in this paper. The relative strength of RHRD12T is estimated by comparing it with other contemporary cells such as NS10T, PS10T, RHBD10T, QUATRO12T, QUCCE12T, and RHD12T on various major design metrics. Due to the read-decoupled nature of RHRD12T, it shows the highest read stability. It also consumes the lowest hold power compared to all other considered cells, except NS10T. Moreover, RHRD12T exhibits the highest write ability due to the use of two extra access transistors and the poor driving ability of the internal nodes. In terms of write delay, RHRD12T shows an improvement of 1.02Â/1.06Â/1.07Â/1.08Â over NS10T/RHD12T/PS10T/RHBD10T at V DD = 1 V. Moreover, RHRD12T is capable of tolerating the highest amount of critical charge among all other comparison cells and is the least susceptible to single-event upsets. All the aforementioned improvements are obtained at the cost of longer read delay. K E Y W O R D Sdigital circuit, low power design, memory design, read stability, SRAM | INTRODUCTIONSatellites have become an integral part of human society, as we rely on satellite communication for a wide range of services, from meteorology to disaster monitoring, from navigation systems to military operations, and so on. 1 As the technology is advancing, lightweight satellites are replacing heavyweight satellites because of their higher manufacturing cost. 2 Since lightweight satellites have limited resources, they require high-density memory cells, and static random-access memory (SRAM) cells are the best alternative for space applications because of their high packing density and improved logic performance. 1 Space presents extreme conditions, like temperature fluctuations and radiation. Due to the weak geomagnetic field in space, radiation and energized particles increase. To withstand this harsh environment, special electronic components and circuits are used. Once a radiation particle strikes a logic circuit at its sensitive node, it generates electron-hole pairs (Figure 1A). These pairs become separated and accumulate at the sensitive node. 3 The accumulated charge at the sensitive node then generates a transient voltage pulse. If enough charge (i.e., critical charge, Q C ) is

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A highly stable reliable SRAM cell design for low power applications

Cited by 42 publications

References 42 publications

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

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