A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications

Hosseini, Seyed Rasool; Saberi, Mehdi; Lotfi, Reza

doi:10.1109/tvlsi.2016.2604377

Cited by 46 publications

(17 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, the area penalty of using both LVT and 3V devices under 180nm CMOS process becomes negligible under better manufacturing capability to fabricate the LVT and 3V devices in advanced CMOS technologies. Table 2 presents the performance of our proposed architecture and the state-of-the-art level-shifters [8], [17], [19]- [22]. Similar to the evaluation methods used in [31], [32] to evaluate the state-of-art works, we have optimized the transistors' size of all circuits to achieve optimal delay, power consumption and silicon area.…”

Section: Benchmark and Discussionmentioning

confidence: 99%

“…In these applications, some of the circuits are usually working with an ultra-low supply voltage of 200mV or even below and an operation frequency of several kilohertz to reduce the power consumption while the remaining circuits are operating at nominal supply voltage and the interface circuits through I/O are operating at a supply voltage ranging from 2.5 to 3.0V. Therefore, it is crucial for a level-shifter to convert the signals near the ultralow supply voltage to a wide output voltage range from the nominal supply voltage (1.2V) to I/O supply voltage (3V) [8]- [23]. Fig.…”

Section: Introductionmentioning

confidence: 99%

“…Consequently, the output node Q will be pulled to VSS/VDDH by NM3/PM3 when q2 is VDDH/VSS. The proper functionality of a conventional DCVS level-shifter is highly dependent on the driving strength ratio between the N-type transistor NM1/NM2 and P-type transistor PM1/PM2 [8]. When the level-shifter is operating at an ultra-low supply voltage, VDDL, the N-type transistors are operating in the sub-threshold region, resulting in a significant reduction of the driving strength.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Sub-100mV Ultra-Low Voltage Level-Shifter Using Current Limiting Cross-Coupled Technique for Wide-Range Conversion to I/O Voltage

et al. 2020

View full text Add to dashboard Cite

In this paper, a sub-100mV ultra-low-voltage level-shifter for wide-range voltage conversion to I/O voltage is presented. The level-shifter uses a current limiting diode-connected transistor with crosscoupled transistor structure to reduce the minimum input voltage down to 100mV while covering a wide output voltage range up to I/O supply voltage (3V). We propose an improved split-control output buffer to reduce the static current from VDDH to VSS. The level-shifter is implemented using X-FAB 180nm HV CMOS process. The post-layout simulations show that the proposed structure achieves an average propagation delay of 7.57µs with a power consumption of 3.43nW when the supply voltages VDDL, VDDH, and input frequency are 100mV, 3V, and 1kHz, respectively. The design occupies 182.46µm 2 silicon area with a static power consumption of 3nW when VDDL and VDDH are 100mV and 3V, respectively, which is suitable for low power applications. INDEX TERMS Differential cascode voltage switch, level-shifter, low power, sub-threshold voltage, wide voltage range

show abstract

Section: Benchmark and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Sub-100mV Ultra-Low Voltage Level-Shifter Using Current Limiting Cross-Coupled Technique for Wide-Range Conversion to I/O Voltage

et al. 2020

View full text Add to dashboard Cite

show abstract

“…To realize robust conversions between large supply voltage differences, several level shifters have been proposed [15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32]. In order to balance the strength of the pull-up and pull-down networks in cross-coupled based level shifter, in [18,26], diode current limiters are inserted in the pull-up networks to reduce the pull-up strength.…”

Section: Introductionmentioning

confidence: 99%

“…Another way to reduce the strength of pull-up networks is to insert current generators in pull-up networks shown in [23]. As for the large standby power of the current-mirror based level shifter, feedback circuits are usually inserted to cut-off the static on-current [16,21,22,25,28,31].…”

Section: Introductionmentioning

confidence: 99%

An ultra-low leakage energy efficient level shifter with wide conversion range

You

Jia

Tang

et al. 2019

IEICE Electron. Express

View full text Add to dashboard Cite

An ultra-low leakage energy efficient level shifter that can convert extremely low input voltage into the supply voltage level is presented in this paper. In order to reduce the leakage power dissipation, the super-cutoff mechanism and MTCMOS technique are utilized in the proposed structure. At the same time, a positive feedback circuit is inserted to avoid the loss of performance. Post-layout simulation results in a 55-nm MTCMOS process demonstrate that for the voltage level conversion from 0.3 V to 1.2 V, the proposed level shifter exhibits a propagation delay of 70.77 ns and an energy per transition of 89.55 fJ for input frequency of 1 MHz. Meanwhile, the static power of the proposed level shifter is as low as 27.82 pW. The proposed level shifter only occupies 7.79 um 2 , which demonstrates prominent area efficiency.

show abstract

Power‐efficient voltage up level shifter with low power–delay product

Fayaz

Rao

2021

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryIn this article, a power‐efficient hybrid voltage up level shifter (LS) is designed. By using a combination of a current mirror (CM) and a cross‐coupled pMOS pair in a pull‐up circuitry, the dynamic power is reduced significantly even at boosted switching speed. The designed LS circuit, which occupies a small silicon area, consists of 10 transistors and is mainly suitable for ultra‐low‐power applications, such as wireless sensor nodes and biomedical appliances. Moreover, it can convert extreme low‐level input voltages to the high supply voltage levels. The results obtained from post‐layout simulations in a standard 180‐nm CMOS process illustrate that the designed LS circuit has total power consumption, static power dissipation, and propagation delay of 33.93 nW, 253 pW, and 9.09 ns, respectively, at 1 MHz with a minimum supply voltage (VDDL) of 0.4 V and nominal supply voltage (VDDH) of 1.8 V. Also, the designed LS can convert an input voltage of 0.12–1.8 V at 10 kHz.

show abstract

A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications

Cited by 46 publications

References 9 publications

A Sub-100mV Ultra-Low Voltage Level-Shifter Using Current Limiting Cross-Coupled Technique for Wide-Range Conversion to I/O Voltage

A Sub-100mV Ultra-Low Voltage Level-Shifter Using Current Limiting Cross-Coupled Technique for Wide-Range Conversion to I/O Voltage

An ultra-low leakage energy efficient level shifter with wide conversion range

Power‐efficient voltage up level shifter with low power–delay product

Contact Info

Product

Resources

About