A Fast Approach for Generating Efficient Parsers on FPGAs

Abstract

The development of modern networking requires that high-performance network processors be designed quickly and efficiently to support new protocols. As a very important part of the processor, the parser parses the headers of the packets—this is the precondition for further processing and finally forwarding these packets. This paper presents a framework designed to transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays (FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler. The hardware architecture comprises many components with varying functionality, each of which has its own optimized VHDL template. By using the output of a standard frontend P4 compiler, our proposed compiler extracts the parameters and relationships from within the used components, which can then be mapped to corresponding templates by configuring, optimizing, and instantiating them. Finally, these templates are connected to output VHDL code. When a prototype of this framework is implemented and evaluated, the results demonstrate that the throughputs of the generated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with state-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when similar amounts of resources are being used.

P4 to FPGA-A Fast Approach for Generating Efficient Network Processors

“…This parser is designed and scheduled based on the supported network protocols, and each pipeline stage in the parser processes one protocol in each cycle. A previous version of this idea was presented in [33]; we will briefly review it and add new material regarding the ''external'' function to the pipeline scheduling in this section.…”

HP4 High-Performance Programmable Packet Parser

“…Therefore, there is a need for a prodigious packet parser at all modern network infrastructure [1]. However, many problems are facing the design and the implementation of the parser such as (1) processing at a line rate in the high-speed network (parsing millions of packets per second), (2) adaptation to new protocols; the number and types of protocol types are varied (adding a new protocol needs an experienced designer acclimated to the HDL language or parser architecture), (3) incomplete information (some protocols have more one format: standard and customized), (4) the header fields attributes (number, size, and location) varied with the protocol type, (5) the parser must have a small size because of the restriction of the programmable device's size, and (6) the enormous hole between the product description and the hardware implementation in the device of new types protocol. These problems demand a programmable hardware packet parsing [2], [3].…”

“…These problems demand a programmable hardware packet parsing [2], [3]. Programmable packet parser relies on three steps: (1) highlevel protocol description, (2) automatic code generation, (3) dynamic reconfigurations. Therefore, the proposed system is a High-Performance Programmable Packet Parser (HP4).…”

“…It has two versions. P416 released in 2017 with a new feature to overcome the limitation of P414 [1]. HP4 used P416.…”

“…So P4 enables a new generation of networking hardware programming that can be dynamic reconfiguration and independent target. FPGAs are the best target platform for P4 programs at hardware line rates [1], [5], [6]. FPGA is a complete framework on a chip, including memory blocks, multiplier, accumulator units, and embedded processors.…”