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The realm of Hardware-in-the-Loop (HIL) simulation resorts to Field Programmable Gate Arrays (FPGAs) to achieve time-steps below 1 µs. Such low time-steps are of importance for the aerospace and automotive industries, where power converters have their switching frequencies in the 10-200 kHz range. This article proposes a Network Tearing Technique (NTT) that allows subsets of switches to be treated independently, alleviates embedded memory requirements, and reduces the computational burden. An iterative algorithm is used to determine the state of naturally commutated switches, thus offering a realistic model of the power converter, independently of its operation mode or topology. A Gauss-Jordan processing unit is implemented to solve interface voltages/currents from the torn circuit. Custom floating-point operators are used to ensure good accuracy, high frequency operation as well as low computational latency. A neutral-point-clamped (NPC) converter case study is presented to demonstrate the effectiveness of the method. Simulation results are validated against a reference model at a 750 ns time-step and 30 kHz Sine Pulse Width Modulation (SPWM) switching frequency.

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