Misfolded endoplasmic reticulum (ER) proteins are retro-translocated through the membrane into the cytosol, where they are poly-ubiquitinated, extracted from the ER membrane, and degraded by the proteasome 1–4, a pathway termed ER-associated protein degradation (ERAD). Proteins with misfolded domains in the ER lumen or membrane are discarded through the ERAD-L and –M pathways, respectively. In S. cerevisiae, both pathways require the ubiquitin ligase Hrd1, a multi-spanning membrane protein with a cytosolic RING finger domain 5,6. Hrd1 is the crucial membrane component for retro-translocation 7,8, but whether it forms a protein-conducting channel is unclear. Here, we report a cryo-electron microscopy (cryo-EM) structure of S. cerevisiae Hrd1 in complex with its ER luminal binding partner Hrd3. Hrd1 forms a dimer within the membrane with one or two Hrd3 molecules associated at its luminal side. Each Hrd1 molecule has eight trans-membrane segments, five of which form an aqueous cavity extending from the cytosol almost to the ER lumen, while a segment of the neighboring Hrd1 molecule forms a lateral seal. The aqueous cavity and lateral gate are reminiscent of features in protein-conducting conduits that facilitate polypeptide movement in the opposite direction, i.e. from the cytosol into or across membranes 9–11. Our results suggest that Hrd1 forms a retro-translocation channel for the movement of misfolded polypeptides through the ER membrane.
Through reorganizing the execution order and optimizing the data structure, we proposed an efficient parallel framework for H.264/AVC encoder based on massively parallel architecture. We implemented the proposed framework by CUDA on NVIDIA's GPU. Not only the compute intensive components of the H.264 encoder are parallelized but also the control intensive components are realized effectively, such as CAVLC and deblocking filter. In addition, we proposed serial optimization methods, including the multiresolution multiwindow for motion estimation, multilevel parallel strategy to enhance the parallelism of intracoding as much as possible, component-based parallel CAVLC, and direction-priority deblocking filter. More than 96% of workload of H.264 encoder is offloaded to GPU. Experimental results show that the parallel implementation outperforms the serial program by 20 times of speedup ratio and satisfies the requirement of the real-time HD encoding of 30 fps. The loss of PSNR is from 0.14 dB to 0.77 dB, when keeping the same bitrate. Through the analysis to the kernels, we found that speedup ratios of the compute intensive algorithms are proportional with the computation power of the GPU. However, the performance of the control intensive parts (CAVLC) is much related to the memory bandwidth, which gives an insight for new architecture design.
Numerical simulation of subcellular Ca 2 + dynamics with a resolution down to one nanometre can be an important tool for discovering the physiological cause of many heart diseases. The requirement of enormous computational power, however, has made such simulations prohibitive so far. By using up to 12,288 Intel Xeon Phi 31S1P coprocessors on the new hybrid cluster Tianhe-2, which is the new number one supercomputer of the world, we have achieved 1.27 Pflop/s in double precision, which brings us much closer to the nanometre resolution. This is the result of efficiently using the hardware on different levels: (1) a single Xeon Phi (2) a single compute node that consists of a host and three coprocessors, and (3) a huge number of interconnected nodes. To overcome the challenge of programming Intel’s new many-integrated core (MIC) architecture, we have adopted techniques such as vectorization, hierarchical data blocking, register data reuse, offloading computations to the coprocessors, and pipelining computations with intra-/inter-node communications.
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