A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission

Cui, Delong; Raghavan, Bharath; Singh, Ullas; Vasani, Anand; Huang, Zhi; Pi, Deyi; Khanpour, M.; Nazemi, Ali; Maarefi, Hassan; Zhang, Wei; Ali, Tamer; Huang, Nick; Zhang, Bo; Momtaz, Afshin; Cao, Jun

doi:10.1109/jssc.2012.2216451

Cited by 12 publications

(7 citation statements)

References 13 publications

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“…20 will have a narrower distribution and the BER performance will be increased more. If the number keeps increasing, then (18) can be expected to eventually arrive at ideal (14). However, in this design, eight is the maximum number of delay cells in the given technology with reasonable power dissipation.…”

Section: B Practical Bit Error Rate Analysis For the Jtementioning

confidence: 99%

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

Hwang

Song

Bae

et al. 2016

IEEE Trans. VLSI Syst.

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An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-of-band JTOL of 0.71 UI pp at 100 MHz with <10 −12 BER. This is 196% higher than a conventional receiver without the JTE. The source-synchronous receiver with the proposed JTE achieved 0.92 UI pp at 300 MHz with <10 −12 BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm 2 in a 0.13-µm CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW.Index Terms-Bit error rate (BER), jitter tolerance (JTOL), real-time jitter tolerance enhancer (JTE), receiver (Rx).

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Section: B Practical Bit Error Rate Analysis For the Jtementioning

confidence: 99%

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

Hwang

Song

Bae

et al. 2016

IEEE Trans. VLSI Syst.

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show abstract

“…Each unit cell has eight separate differential pairs that share the same input and output but have individual tail current source. In this way, both the differential pair and current source can be switched on and the coefficients of A and B (voltage gain of the differential-pair circuit) are proportional to the numbers of differential pairs that are switched ON [24]. To produce 64 outputs over (0, 2π), as shown in Fig.…”

Section: A Two-step Phase Interpolatormentioning

confidence: 99%

A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator

Huang

et al. 2024

IEEE Trans. VLSI Syst.

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An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new, low-power and two-step PI with high linearity over 4-8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme, which enables continuous data rate support. The digital architecture not only eliminates the large filtering capacitor, but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm 2 in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. Measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the SONET OC-192 jitter tolerance mask at least by 0.2 UI at high frequencies (4-100 MHz), with 2 31 − 1 pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of 10 −12 .Index Terms-All-digital, clock and data recovery (CDR), dithering jitter, high linearity, jitter tolerance (JTOL), low-pass filter (LPF), multimode phase detection, phase interpolator (PI), wideband.

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“…To guarantee the serialized data with low jitter performance, the 25% duty cycle clock pulse must have sharp edges to drive the output transistor in every clock period. In [17], [22], [23], a large-size inverter is employed to provide steep transition edges, which is power hungry. Fig.…”

Section: :1 Muxmentioning

confidence: 99%

“…2(b). These analog delay lines are usually based on cascaded CML buffers [17], [18], or LC-cells [2], [19]- [21], which have been proved in ultra-high-speed applications such as 64 Gb/s [2]. Nonetheless, they cannot support a wide operation range because of their limited adjusting range.…”

Section: Introductionmentioning

confidence: 99%

A 2-40 Gb/s PAM4/NRZ Dual-mode Wireline Transmitter with 4:1 MUX in 65-nm CMOS

Lv¹,

Zheng²,

Zhao³

et al. 2018

JSTS

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A 2-40 Gb/s PAM4/NRZ dual-mode wireline transmitter with 4:1 MUX in 65-nm CMOS http://researchonline.ljmu.ac.uk/8698/ Article LJMU has developed LJMU Research Online for users to access the research output of the University more effectively.Abstract-This paper presents a 2-40 Gb/s dual-mode wireline transmitter supporting the four-level pulse amplitude modulation (PAM4) and non-return-tozero (NRZ) modulation with a multiplexer (MUX)based two-tap feed-forward equalizer (FFE). An edgeacceleration technique is proposed for the 4:1 MUX to increase the bandwidth. By utilizing a dedicated cascode current source, the output swing can achieve 900 mV with a level deviation of only 0.12% for PAM4. Fabricated in a 65-nm CMOS process, the transmitter consumes 117 mW and 89 mW at 40 Gb/s in PAM4 and NRZ at 1.2 V supply. Index Terms-Four-level pulse amplitude modulation (PAM4), non-return-to-zero (NRZ), edge-acceleration technique, linearity optimization, dual-mode wireline transmitter

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A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission

Cited by 12 publications

References 13 publications

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator

A 2-40 Gb/s PAM4/NRZ Dual-mode Wireline Transmitter with 4:1 MUX in 65-nm CMOS

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