A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator

Abstract

An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new, low-power and two-step PI with high linearity over 4-8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme, which enables continuous data rate support. The digital architecture not only eliminates the large filtering capacitor, but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm 2 in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. Measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the SONET OC-192 jitter tolerance mask at least by 0.2 UI at high frequencies (4-100 MHz), with 2 31 − 1 pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of 10 −12 .Index Terms-All-digital, clock and data recovery (CDR), dithering jitter, high linearity, jitter tolerance (JTOL), low-pass filter (LPF), multimode phase detection, phase interpolator (PI), wideband.

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

“…27. Finally, apart from [9] and [11] which have the unattractive requirement that they need a tunable, high-quality, multi-gigahertz frequency reference clock, our design has the highest relative frequency range for digital CDRs. …”

A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

“…A PI can potentially replace a digital-to-time converter (DTC) in many applications to generate a time delay. Several PI topologies have been proposed; Delay line based [6], [7], trigonometric [2], [8], [9], current-weighting [1], [3], [4], [10], [11], charge-steering [12] and constant-slope charging [5], [13].…”

Synthesisable glitch‐less phase rotator with conditionally cascading scheme

“…Introduction: A phase rotator (PR) is a circuit component that is widely used in wireline interface applications such as clock and data recoveries (CDRs) [1][2][3][4][5]. CDRs with a forwarded reference clock require a PR after a multiphase clock generator to recover the clock phase of the data sampling point [2,3,5], thus the performance of such CDRs varies with that of the PR. PRs are commonly realised in the current-mode logic (CML) to achieve high linearity and a wide frequency range.…”

“…PRs are commonly realised in the current-mode logic (CML) to achieve high linearity and a wide frequency range. However, such a topology consumes large power owing to the static current and requires a large silicon area due to the passive loads [2][3][4]. Another PR implementation is made up of inverter buffers with configurable driving strength [5].…”

“…Furthermore, recent researchers have attempted to implement building blocks of CDRs in highly digital-friendly manners to enable scalable and portable designs [2,6]. This Letter aids such attempts by providing a solution for synthesising a PR through the automatic design flow.…”