A comparative study of the effect of dynamic stressing on high-field endurance and stability of reoxidized-nitrided, fluorinated and conventional oxides

Liu, Z.H.; Rosenbaum, Elyse; Ko, P.K.; Hu, Chenming; Cheng, Yaqi; Sodini, C.G.; Groß, Bernhard; Ma, T.P.

doi:10.1109/iedm.1991.235321

Cited by 5 publications

(5 citation statements)

References 9 publications

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“…We confirmed that, for example, the durations for which the voltages exceed 10V are at most 0.3ns. Therefore it may be inferred that the gate oxides won't be damaged in the early stage of discharge [11].…”

Section: Voltages Across the Gate Oxides In The Early Stage Of Dischargementioning

confidence: 99%

A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices

Choi¹

2010

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For three fundamental input-protection schemes suitable for high-frequency CMOS ICs, which utilize protection devices such as NMOS transistors, thyristors, and diodes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit model of input HBM test environments for CMOS chips equipped with input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the peak voltage developed in the later stage of discharge, which corresponds to the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain strength and weakness of each protection scheme as an input ESD protection circuit for high-frequency ICs, and suggest valuable guidelines relating design of the protection devices and circuits

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Section: Voltages Across the Gate Oxides In The Early Stage Of Dischargementioning

confidence: 99%

A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices

Choi¹

2010

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“…It has been shown that hole trapping is correlated with oxide breakdown [4]. A hole trapping/migration model has been proposed to explain the increased lifetime under high-frequency stress observed for reoxidized ",-nitrided oxides [3]. According to this model, there exist two competing mechanisms: first, the hole trapping rate which will decrease with frequency due to detrapping by tunneling, and second, the drift distance of the trapped hole from the anode which will also decrease with frequency.…”

Section: Discussion and Resultsmentioning

confidence: 99%

“…One of the reasons for G, degradation is the increase in Dit which leads to channel mobility decrease [3]. To examine ADit as a function of frequency, the chargepumping technique is used and AZcpmax, the increase in the maximum charge-pumping current as 5 is varied, is plotted in Fig.…”

Section: Discussion and Resultsmentioning

confidence: 99%

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Degradation of N/sub 2/O-annealed MOSFET characteristics in response to dynamic oxide stressing

Chen

Liu

Krick

et al. 1993

IEEE Electron Device Lett.

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The performance of n-MOSFETs with furnace N,O-annealed gate oxides under dynamic Fowler-Nordheim bipolar stress was studied and compared with that of conventional oxide (OX). Time-dependent dielectric breakdown at high frequency was shown to be improved for the N,O-annealed devices compared with that for devices with OX. In addition, a smaller V, shift for nitrided samples after stress was found. The shift decreased with increasing stressing frequency and annealing temperature. Measurements of both G , and Dit revealed a "peak" frequency at which the degradation was the worst. A hole trapping/migration model has been proposed to explain this.

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“…We confirmed that, for example, the durations for which the voltages exceed 10 V are at most 0.2 ns. Therefore it may be inferred that the gate oxides in the input buffer won't be damaged in the early stage of discharge [11].…”

Section: Voltages Across the Gate Oxides In The Early Stage Of Dischargementioning

confidence: 99%

A Thyristor-Only Input ESD Protection Scheme for CMOS RF ICs

Choi¹,

Park²

2011

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We propose an input protection scheme composed of thyristor devices only without using a clamp NMOS device in order to minimize the area consumed by a pad structure in CMOS RF ICs. For this purpose, we suggest low-voltage triggering thyristor protection device structures assuming usage of standard CMOS processes, and attempt an in-depth comparison study with a conventional thyristor protection scheme incorporating a clamp NMOS device. The comparison study mainly focuses on robustness against the HBM ESD in terms of peak voltages applied to gate oxides in an input buffer and lattice heating inside protection devices based on DC and mixed-mode transient analyses utilizing a 2-dimensional device simulator. We constructed an equivalent circuit for the input HBM test environment of the CMOS chip equipped with the input ESD protection devices. And by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can occur in real HBM tests. We figure out strength of the proposed thyristor-only protection scheme, and suggest guidelines relating the design of the protection devices and circuits

show abstract

A comparative study of the effect of dynamic stressing on high-field endurance and stability of reoxidized-nitrided, fluorinated and conventional oxides

Cited by 5 publications

References 9 publications

A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices

A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices

Degradation of N/sub 2/O-annealed MOSFET characteristics in response to dynamic oxide stressing

A Thyristor-Only Input ESD Protection Scheme for CMOS RF ICs

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