A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices

Abstract

For three fundamental input-protection schemes suitable for high-frequency CMOS ICs, which utilize protection devices such as NMOS transistors, thyristors, and diodes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit model of input HBM test environments for CMOS chips equipped with input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the peak voltage developed in the later stage of discharge, which corresponds to the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain strength and weakness of each protection scheme as an input ESD protection circuit for high-frequency ICs, and suggest valuable guidelines relating design of the protection devices and circuits

Discharge Characteristics of a Triple-Well Diode-String ESD Clamp

“…In the early stage of discharge, the voltage on C ngate shown in Figure 8 peaks up to 14.9V for a very short duration in the range of a few nanoseconds, which is regarded as not harmful to the gate oxides of the input buffer [5]. This voltage Figure 7.…”

“…C ESD and R ESD represent a human capacitance and a human contact resistance, respectively. Values for other parasitic elements are described in [5]. V ESD is a HBM test voltage, and a switch S1 charges C ESD and then a switch S 2 initiates discharge.…”

“…Diode strings can reduce the V DD -V SS clamping voltage since the number of diodes in series connection will determine the forward turn-on voltage during an ESD event. Since there is no snapback behavior in these devices which appears in NMOS devices, there is no danger of inducing large voltages on gate oxides of input buffers for long time [5].…”

“…In Figure 1, a CMOS inverter is assumed as an input buffer. In Figure 1, the discharge path for a PS mode is shown, which is regarded as the weakest mode among HBM discharge events [5]. A PS mode represents the test mode, where a positive ESD voltage is applied to an input pin with a V SS pin grounded.…”

“…In a diode input protection scheme utilizing an NMOS clamp device, critical peak voltages developed across gate oxides of an input buffer in an ESD event are determined by the sum of the forward voltage drop across the diode device and the V DD -V SS clamping voltage, which is equal to the snapback voltage of the NMOS clamp device [5]. Hence, as gate oxides are getting thinner, the snapback voltage, which cannot be engineered much, becomes an obstacle in using the NMOS clamp device further.…”