This paper examines the recently introduced chargebased capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure.
This paper examines the recently introduced ChargeBased Capacitance Measurement (CBCM) technique through use of a 3-D interconnect simulator. This method is shown to have several advantages over extensive computer simulation in determining parasitic interconnect capacitances, which are the dominant source of delay in modern circuits. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure.
IntroductionIn the past, circuit delay has been due mostly to transistors. For this reason, much effort is put into device scaling. Today, the dominant source of delay in circuits such as ASIC's and microprocessors is metal interconnect. As interconnect scales with each technology generation, several tradeoffs are made. In order to reduce line resistance and improve electromigration properties, metal height is kept fairly constant, and not scaled with pitch. The increasing aspect ratio (heighvpitch) results in larger coupling capacitances and more crosstalk. This problem worsens as more metal layers are added with almost every generation. The performance gains of adding more metallization layers will soon saturate; in other words, a limit exists for the number of metal layers feasible for integrated circuits. Once this limit is reached, only tighter pitches in each layer will result in higher density, leading to larger capacitances again [I].From these points, it can be seen that interconnect capacitance characterization is an important aspect of current and future process development as well as circuit design. In order to give circuit designers an accurate assessment of speed and noise issues, parasitic capacitances due to interconnect must be well described. Currently, this is done with extensive computer simulation. A new, measurement-based technique, Charge-Based Capacitance Measurement (CBCM) [2], has been developed to characterize interconnect capacitances. This simple, compact, and sensitive test structure can be used to measure any interconnect capacitance structure. In this paper, we will com-
The performance of n-MOSFETs with furnace N,O-annealed gate oxides under dynamic Fowler-Nordheim bipolar stress was studied and compared with that of conventional oxide (OX). Time-dependent dielectric breakdown at high frequency was shown to be improved for the N,O-annealed devices compared with that for devices with OX. In addition, a smaller V, shift for nitrided samples after stress was found. The shift decreased with increasing stressing frequency and annealing temperature. Measurements of both G , and Dit revealed a "peak" frequency at which the degradation was the worst. A hole trapping/migration model has been proposed to explain this.
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