A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection

Lin, Wen-Jeng; Kuo, Tai‐Haur

doi:10.1109/jssc.2011.2168651

Cited by 77 publications

(42 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Another choice is the use of calibration techniques with additional costs [9], [17]. The third choice is the Dynamic Element Matching (DEM), which has been widely adopted to make DAC outputs insensitive to transistor mismatch for higher SFDR performance while maintaining smaller chip area without calibration costs [1], [2], [10]. Furthermore, by modulating the switching activities of the current sources randomly, DEM is also effective in SFDR improvement through randomizing the switching glitches and thus suppressing the harmonic distortions [10].…”

Section: Proposed Tri-demrz Techniquementioning

confidence: 99%

“…Current-steering digital-to-analog converters (DACs) with a high resolution and a high sampling rate have been widely used with increasing spectrum performance requirement such as the spurious-free dynamic range (SFDR) [1]- [7]. Fig.…”

Section: Introductionmentioning

confidence: 99%

“…For high-speed DACs, the current source mismatches [1], [2], [8]- [10], code-dependent load variations [3]- [5], [11] and code-dependent switching glitches [2]- [4], [7] are the main issues that limit the SFDR. At higher frequencies, the finite output impedance due to parasitics worsens the code-dependent load variation and deteriorates the SFDR.…”

Section: Introductionmentioning

confidence: 99%

“…A smaller currentsource transistor can be adopted for less parasitics but will do harm to the matching performance of the current sources [2]. Dynamic element matching (DEM) has been a solution to using smaller-sized transistors while maintaining good matching properties and achieving better SFDR, as its randomized decoder mitigates not only the current source mismatch but also the effect of the code-dependent switching glitches [1], [2], [10].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

Liu

Wei

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

A 14-bit 1.0-GS/s current-steering digital-to-analog converter (DAC) was designed in a 65-nm CMOS process. For such current-steering DACs with a high sampling rate, the codedependent load variations and switching glitches are a main bottleneck which limits the spurious-free dynamic range (SFDR). Dynamic element matching (DEM) has been an effective solution to randomize these glitches for a higher SFDR and also to reduce the matching requirement of the current cells for an areaefficient design which also improves the SFDR with reduced parasitic capacitance. An effective method named TRI-DEMRZ is proposed in this paper, consisting of time-relaxed interleaving, DEM and return-to-zero encoding. We also apply TRI-DEMRZ in synergy with complementary switched current sources (CSCS) to design the DAC for the purpose of a small die size and enhanced SFDR performance. Post-layout simulations show >80 dB SFDR up to the Nyquist. This DAC has a mixed 1.2 V / 2.5 V power supply and an active area of 0.48 mm 2 . Keywords-Digital-to-analog converter (DAC); mismatch; Dynamic element matching (DEM); return-to-zero (RZ); spuriousfree dynamic range (SFDR)I.978-1-4799-8391-9/15/$31.00 ©2015 IEEE

show abstract

Section: Proposed Tri-demrz Techniquementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

Liu

Wei

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…By randomizing which unit cells are used at any time to create a binary scaled source, [57] can decrease the mismatch induced distortion components. In [58] an active calibration is used to reorder the switching sequence such that the INL is optimized: a smaller-than-nominal current cell will be followed by a larger-than-nominal one.…”

Section: Other Publicationsmentioning

confidence: 99%

Time-interleaved high speed D/A converters

Olieman¹

View full text Add to dashboard Cite

Intersegment mismatch mitigation with multidimensional dynamic element matching digital to analog converters

Babaei

Hashemipour

2020

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryIn this paper, a two‐dimensional dynamic element matching digital to analog converter (2D DEM DAC) is proposed having less design complexity compared to the conventional 2D DEM DAC. A novel unit element selection algorithm is presented in order to alleviate the need for consecutive elements selection that is mandatory in the conventional 2D DEM DAC. The flexibility of this algorithm leads to the introduction of a generalized multidimensional DEM DAC applicable to any resolutions. The multidimensional structure mitigates intersegment mismatch error and improves the spurious‐free dynamic range (SFDR) and intermodulation distortion (IMD). A 12‐bit 2D DEM DAC is simulated in 65‐nm CMOS process using the digital return‐to‐zero (DRZ) technique with 1.2 V of supply voltage and power dissipation of 26 mW. The simulation results show 63.4‐ and 60.71‐dB SFDR at near DC and Nyquist frequency, respectively, and <−61‐dB IMD with 1.25‐GHz sampling frequency.

show abstract

A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection

Cited by 77 publications

References 16 publications

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

Time-interleaved high speed D/A converters

Intersegment mismatch mitigation with multidimensional dynamic element matching digital to analog converters

Contact Info

Product

Resources

About

A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection

Cited by 77 publications

References 16 publications

A 14-bit 1.0-GS/s dynamic element matching DAC with &#x003E;80 dB SFDR up to the Nyquist

A 14-bit 1.0-GS/s dynamic element matching DAC with &#x003E;80 dB SFDR up to the Nyquist

Time-interleaved high speed D/A converters

Intersegment mismatch mitigation with multidimensional dynamic element matching digital to analog converters

Contact Info

Product

Resources

About

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist