SummaryIn this paper, a two‐dimensional dynamic element matching digital to analog converter (2D DEM DAC) is proposed having less design complexity compared to the conventional 2D DEM DAC. A novel unit element selection algorithm is presented in order to alleviate the need for consecutive elements selection that is mandatory in the conventional 2D DEM DAC. The flexibility of this algorithm leads to the introduction of a generalized multidimensional DEM DAC applicable to any resolutions. The multidimensional structure mitigates intersegment mismatch error and improves the spurious‐free dynamic range (SFDR) and intermodulation distortion (IMD). A 12‐bit 2D DEM DAC is simulated in 65‐nm CMOS process using the digital return‐to‐zero (DRZ) technique with 1.2 V of supply voltage and power dissipation of 26 mW. The simulation results show 63.4‐ and 60.71‐dB SFDR at near DC and Nyquist frequency, respectively, and <−61‐dB IMD with 1.25‐GHz sampling frequency.
Summary
In this paper, a method for 3
k‐th (
k∈double-struckN) harmonics rejection in 6
N‐path filters is proposed, and the related analysis is provided. Using a single‐ended‐input to differential‐output structure, the filter selectivity around even harmonics are also suppressed. Accordingly, a proof‐of‐concept band‐pass filter is designed, and postlayout simulations in the 90‐nm CMOS technology are carried out, which covers an input frequency range from 200 MHz to 1.2 GHz with a channel bandwidth of 10 to 15.5 MHz. The achieved third harmonic rejection at 1‐GHz local oscillator (LO) frequency is about 43 dB. Over the entire radio frequency (RF) range, the in‐band IIP3 and noise figure are better than
−1.5 dBm and 5.3 dB, respectively. The power consumption of the analog circuitry is 21 mW from the 1.2‐V supply, whereas the digital clock generation circuitry consumes between 0.9 and 5.2 mW, depending on the center frequency of the filter.
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