Summary
In this paper, a method for 3
k‐th (
k∈double-struckN) harmonics rejection in 6
N‐path filters is proposed, and the related analysis is provided. Using a single‐ended‐input to differential‐output structure, the filter selectivity around even harmonics are also suppressed. Accordingly, a proof‐of‐concept band‐pass filter is designed, and postlayout simulations in the 90‐nm CMOS technology are carried out, which covers an input frequency range from 200 MHz to 1.2 GHz with a channel bandwidth of 10 to 15.5 MHz. The achieved third harmonic rejection at 1‐GHz local oscillator (LO) frequency is about 43 dB. Over the entire radio frequency (RF) range, the in‐band IIP3 and noise figure are better than
−1.5 dBm and 5.3 dB, respectively. The power consumption of the analog circuitry is 21 mW from the 1.2‐V supply, whereas the digital clock generation circuitry consumes between 0.9 and 5.2 mW, depending on the center frequency of the filter.
SummaryIn this paper, a band‐pass filter with a tunable bandwidth and the center frequency is introduced, which employs N‐path and N × M‐path passive mixer structures, for multiband multistandard wireless receivers. The center frequency of the proposed filter is tunable from 0.1 to 1 GHz, while its bandwidth is also adjustable from 6% to 34% of the center frequency at 100 MHz. The passband ripple is reduced by applying a Miller compensation technique, resulting in a worst‐case ripple of only 1.6 dB over the entire tuning range. An additional eight‐path filter is also utilized at the input of the circuit, which highly improves the out‐of‐band rejection of the filter as well as its out‐of‐band linearity. The noise figure and the input return loss are, respectively, better than 5 and 10 dB, and depending on the desired center frequency, the total power consumption of the proposed filter varies from 41 to 70 mW.
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