A compact AES core with on-line error-detection for FPGA applications with modest hardware resources

Legat, Uroš; Biasizzo, Anton; Novak, Franc

doi:10.1016/j.micpro.2011.03.001

Cited by 16 publications

(10 citation statements)

References 14 publications

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“…We can observe several technique methods for the reliability of AES system. The online error-detection method obtain the highefficiency because there is not extra fault tolerant circuit in this paper [22]. Our results achieved for the throughput, area (slices used and BRAMs), and high-efficiency are very good for a high reliability system array redundancy.…”

Section: S21mentioning

confidence: 65%

Cell array reconfigurable architecture for high-efficiency AES system

Ding

Pan

2012

Microelectronics Reliability

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Section: S21mentioning

confidence: 65%

Cell array reconfigurable architecture for high-efficiency AES system

Ding

Pan

2012

Microelectronics Reliability

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“…Several research studies have been developed on parallel AES hardware implementation targeting fault resilient, e.g. [2,13,[22][23][24]. In [13], a detection approach based on partial duplication, with ∼25% area overhead and negligible throughput degradation, is proposed for the parallel implementation of AES.…”

Section: Parallel Aesmentioning

confidence: 99%

“…the combination of time and hardware redundancies, in the first research, and is based on partial hardware redundancy in the next. Bui et al [2] and Legat et al [24] exploited parallel AES implementation. They picked one 32bit parallel block of AES to have low hardware overhead.…”

Section: Parallel Aesmentioning

confidence: 99%

Practical fault resilient hardware implementations of AES

Sheikhpour

Mahani

Bagheri

2019

IET Circuits, Devices & Systems

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Security is a challenging issue in resource-constrained applications, e.g. in an embedded system. This study focused on practical lightweight fault-tolerant strategies for hardware implementation of Advanced Encryption Standard (AES) to mitigate the-reliability issue of secure architectures. In this work, a-fault-tolerant architecture called configurable fault-tolerant AES (CFTA), and its variants, called robust CFTA (R-CFTA), R-CFTA + , high throughput CFTA (HT-CFTA), HT-CFTA4R, HT-CFTA8R, and HT-CFTA + , are introduced. Proposed approaches exploit the-inherent parallel architecture of AES for employing redundancy at low cost. CFTA and HT-CFTA can tolerate all single permanent and transient faults in the-AES blocks and also all multiple permanent and transient faults in the-same block. R-CFTA upgrades the-fault-tolerant aspect of CFTA and HT-CFTA and it is also able to tolerate all single-and multiple-transient faults in two AES functional blocks during a round. The proof is provided to show the fault masking ability of provided architectures. Furthermore, R-CFTA + and HT-CFTA + , which are suitable for high-security sensitive applications are suggested. In addition, the proposed fault-tolerant designs are implemented on both field programmable gate array and application-specific integrated circuit platforms, and their implementation area, frequency, and throughput are discussed and compared with other related works. Moreover, system-efficiency, as an important design metric, is reported for proposed structures.

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“…There are very limited implementations on combined Look‐Up‐Table‐based AES; mostly, they are designed for 32‐bit datapath . These architectures are asymmetric with inefficient utilization of four BRAMs and two BRAMs , and in addition to this, they have also used extra multiplexers and rearrangement circuitry that not only result in utilization of extra hardware resources but also impose large overheads.…”

Section: Related Workmentioning

confidence: 99%

An efficient single unit T‐box/T⁻¹‐box implementation for 128‐bit AES on FPGA

Kundi

Aziz

Kazmi

2014

Security Comm Networks

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In this paper, we present an area efficient Block RAM (BRAM)‐based single unit design of T‐box/T−1‐box on a Field Programmable Gate Array (FPGA) for combined Advanced Encryption Standard (AES) encryption and decryption. Conventional FPGA designs for T‐box module not only utilize several BRAMs for 16 bytes parallel look‐up operations but also because of asymmetric nature of AES, use separate hardware for T−1‐box unit in decryption process. Alternatively in iterative architecture, BRAM in dual‐port mode configuration takes eight clock cycles to access 16 look‐up operations from a T‐box because of its synchronous nature. Thus, resulting in an unoptimized solution not only in term of FPGA resources but also results in high latency for iterative architecture. Our proposed design uses single symmetric T‐box/T−1‐box table with same set of single resource‐shared hardware for both the encryptor and decryptor and at the same time performs eight look‐up operations from single BRAM in one clock cycle using efficient BRAM switching technique instead of using multirated clocking. Our complete 128‐bit symmetric T‐box/T−1‐box design fits into just 2 BRAMs and 136 Slices. It occupies lowest area reported to date with 50% power saving and highest Throughput Per Slice (TPS) of 10.77. Copyright © 2014 John Wiley & Sons, Ltd.

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A compact AES core with on-line error-detection for FPGA applications with modest hardware resources

Cited by 16 publications

References 14 publications

Cell array reconfigurable architecture for high-efficiency AES system

Cell array reconfigurable architecture for high-efficiency AES system

Practical fault resilient hardware implementations of AES

An efficient single unit T‐box/T⁻¹‐box implementation for 128‐bit AES on FPGA

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A compact AES core with on-line error-detection for FPGA applications with modest hardware resources

Cited by 16 publications

References 14 publications

Cell array reconfigurable architecture for high-efficiency AES system

Cell array reconfigurable architecture for high-efficiency AES system

Practical fault resilient hardware implementations of AES

An efficient single unit T‐box/T−1‐box implementation for 128‐bit AES on FPGA

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Product

Resources

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An efficient single unit T‐box/T⁻¹‐box implementation for 128‐bit AES on FPGA