Cryptographic co-processors are integral to the modern System-on-Chips. Flexibility in such designs serves dual purpose, i.e., it enables acceleration of different essential cryptographic primitives (Encryption/Authentication/Pseudo Random Number Generation (PRNG) ) and also results in design compaction via resource sharing. In this context, a novel resource-shared crypto-coprocessor, named AE$HA-3 is presented, which combines two National Institute of Standards and Technology (NIST) standardized algorithms, i.e., Advance Encryption Standard (AES) and Secure Hash Algorithm-3 (SHA-3). Due to algorithmic dissimilarities, so far no resource-shared implementation enabling AES key scheduling/ enc/dec and SHA-3 has been presented. AE$HA-3 exploits resource-sharing for area reduction, i.e., integration of Look-Up-Tables (I-Tables) for AES enc/dec; logical optimization of Six Input Equation (SixIE) for SHA-3; a Unified XOR Section to carry out both key whitening in AES and SHA-3 transformations. Furthermore, the AES key scheduling was performed using the same resource-shared hardware. The proposed AE$HA-3 on Xilinx Virtex FPGA family results in highest hardware efficiency in terms of Throughput per Slice (TPS), along with a 49.37% area consumption reduction, when compared against the smallest stand-alone implementations presented to date.

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