Security is a challenging issue in resource-constrained applications, e.g. in an embedded system. This study focused on practical lightweight fault-tolerant strategies for hardware implementation of Advanced Encryption Standard (AES) to mitigate the-reliability issue of secure architectures. In this work, a-fault-tolerant architecture called configurable fault-tolerant AES (CFTA), and its variants, called robust CFTA (R-CFTA), R-CFTA + , high throughput CFTA (HT-CFTA), HT-CFTA4R, HT-CFTA8R, and HT-CFTA + , are introduced. Proposed approaches exploit the-inherent parallel architecture of AES for employing redundancy at low cost. CFTA and HT-CFTA can tolerate all single permanent and transient faults in the-AES blocks and also all multiple permanent and transient faults in the-same block. R-CFTA upgrades the-fault-tolerant aspect of CFTA and HT-CFTA and it is also able to tolerate all single-and multiple-transient faults in two AES functional blocks during a round. The proof is provided to show the fault masking ability of provided architectures. Furthermore, R-CFTA + and HT-CFTA + , which are suitable for high-security sensitive applications are suggested. In addition, the proposed fault-tolerant designs are implemented on both field programmable gate array and application-specific integrated circuit platforms, and their implementation area, frequency, and throughput are discussed and compared with other related works. Moreover, system-efficiency, as an important design metric, is reported for proposed structures.
As more and more confidential information is being transmitted securely, the use of cryptographic algorithms is expanded. However, existing cryptographic algorithms are subject to various malicious attacks. Fault injection attack is one of the most effective attacks that are able to extract private information with the inexpensive requirement and short amount of time. AES is a block cipher that is used in many critical applications. Here, a lightweight error-detection architecture for AES has been proposed; the authors call it as high throughput fault-resilient AES (HFA). In the proposed architecture, the authors use parallel AES architecture, which contains four equivalent blocks and split each block into two pipeline stages. The authors have shown that HFA achieves high error-detection rate while keeping overheads reasonable.
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