Practical fault resilient hardware implementations of AES

Sheikhpour, Saeide; Mahani, Ali; Bagheri, Nasour

doi:10.1049/iet-cds.2018.5235

Cited by 9 publications

(18 citation statements)

References 25 publications

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“…However, we compare several details about design techniques and implementation results. The related works [ 39 , 54 ] present their hardware architectures on Virtex-5 technology, whereas [ 40 ] uses Virtex-II devices.…”

Section: Implementation Results and Comparisonsmentioning

confidence: 99%

“…On the one hand, in [ 39 ], a large number of hardware architectures that use the techniques of time and hardware redundancy are reported. The authors use several approaches, from having compact architectures to high performance, but the architectures that interest us directly implement five encryption processes similar to ours.…”

Section: Implementation Results and Comparisonsmentioning

confidence: 99%

“…A fault-tolerant architecture called configurable fault-tolerant AES (CFTA), and its variants are presented in [ 39 ] for the AES block cipher with different key sizes and different pipeline levels to mitigate the reliability issue of secure architectures. It is a fault resilient architecture based on a modified temporal redundancy for the parallel implementation of AES.…”

Section: Related Workmentioning

confidence: 99%

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Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

Algredo‐Badillo

Ramírez-Gutiérrez

Morales-Rosales

et al. 2021

Sensors

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Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outside the vehicle. The AES algorithm has been widely applied to protect communications in onboard networks and outside the vehicle. Hardware implementations use techniques such as iterative, parallel, unrolled, and pipeline architectures. Nevertheless, the use of AES does not guarantee secure communication, because previous works have proved that implementations of secret key cryptosystems, such as AES, in hardware are sensitive to differential fault analysis. Moreover, it has been demonstrated that even a single fault during encryption or decryption could cause a large number of errors in encrypted or decrypted data. Although techniques such as iterative and parallel architectures have been explored for fault detection to protect AES encryption and decryption, it is necessary to explore other techniques such as pipelining. Furthermore, balancing a high throughput, reducing low power consumption, and using fewer hardware resources in the pipeline design are great challenges, and they are more difficult when considering fault detection and correction. In this research, we propose a novel hybrid pipeline hardware architecture focusing on error and fault detection for the AES cryptographic algorithm. The architecture is hybrid because it combines hardware and time redundancy through a pipeline structure, analyzing and balancing the critical path and distributing the processing elements within each stage. The main contribution is to present a pipeline structure for ciphering five times on the same data blocks, implementing a voting module to verify when an error occurs or when output has correct cipher data, optimizing the process, and using a decision tree to reduce the complexity of all combinations required for evaluating. The architecture is analyzed and implemented on several FPGA technologies, and it reports a throughput of 0.479 Gbps and an efficiency of 0.336 Mbps/LUT when a Virtex-7 is used.

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Section: Implementation Results and Comparisonsmentioning

confidence: 99%

Section: Implementation Results and Comparisonsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

Algredo‐Badillo

Ramírez-Gutiérrez

Morales-Rosales

et al. 2021

Sensors

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“…The number of errors that can be tolerated by classical TMR, QMR, [20,27], and our proposed architecture as faulttolerant architectures are compared in Figure 10. -405…”

Section: Implementation Resultsmentioning

confidence: 99%

Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

Sheikhpur

Taheri

Ansari³

et al. 2021

IET Computers & Digital Tech

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Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low-cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32-bit data-path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple-bit (byte) simultaneous faults at each pipeline stage's logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault-masking capability for multiple-bit (byte) faults. Finally, it is shown that the Application-Specific Integrated Circuit implementation of the fault-tolerant architectures using the composite field-based S-box, CFB-AES, and ROMbased S-box, RB-AES allows better area usage, throughput and fault resilience trade-off compared to their counterparts. So, it provides the most appropriate features to be used in highly-secure resource-constraint applications.

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“…It should be noted that the injected errors cause erroneous AES results which make the encrypted message output unreliable. To improve the robustness of the AES implementation, until to date, a few fault detection schemes have been proposed [9][10][11][12][13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

An Efficient AES 32-Bit Architecture Resistant to Fault Attacks

Mestiri¹,

Barraj²,

Mohamed³

et al. 2022

Computers, Materials &Amp; Continua

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The Advanced Encryption Standard cryptographic algorithm, named AES, is implemented in cryptographic circuits to ensure high security level to any system which required confidentiality and secure information exchange. One of the most effective physical attacks against the hardware implementation of AES is fault attacks which can extract secret data. Until now, a several AES fault detection schemes against fault injection attacks have been proposed. In this paper, so as to ensure a high level of security against fault injection attacks, a new efficient fault detection scheme based on the AES architecture modification has been proposed. For this reason, the AES 32-bit round is divided into two half rounds and input and pipeline registers are implemented between them. The proposed scheme is independent of the procedure the AES is implemented. Thus, it can be implemented to secure the pipeline and iterative architectures. To evaluate the robustness of the proposed fault detection scheme against fault injection attacks, we conduct a transient and permanent fault attacks and then we determine the fault detection capability; it is about 99.88585% and 99.9069% for transient and permanent faults respectively. We have modeled the AES fault detection scheme using VHDL hardware language and through hardware FPGA implementation. The FPGA results demonstrate that our scheme can efficiently protect the AES hardware implementation against fault attacks. It can be simply implemented with low complexity. In addition, the FPGA implementation performances prove the low area overhead and the high efficiency and working frequency for the proposed AES detection scheme.

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Practical fault resilient hardware implementations of AES

Cited by 9 publications

References 25 publications

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

An Efficient AES 32-Bit Architecture Resistant to Fault Attacks

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