A built-in self-test and self-diagnosis scheme for embedded SRAM

Wang, Chih-Wea; Wu, Cheng‐Li; Li, Jin-Fu; Wu, Cheng‐Wen; Teng, Tao; Chiu, Kevin Kuan‐Shun; Lin, Hsin‐Piao

doi:10.1109/ats.2000.893601

Cited by 44 publications

(1 citation statement)

References 13 publications

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“…An important part of the SABRE system, for which we have not developed a bio-inspired protection mechanism is the SRAM that stores the program instructions and configuration information in each SMove controller. There exist a number of fault detection methods, with a low hardware overhead, that might be applied to ensure the integrity of this vital resource; for example, Wang et al [32] suggest a BIST circuitry that requires less than a 3% overhead; a low overhead implies that there will be a reduced chance of errors due to the lower surface area for radiation impacts. Further, as all processors contain the same memory, faulty data could be restored from another processor.…”

Section: Methods For Fault Detection In the Test And Repair Systemsmentioning

confidence: 99%

SABRE: a bio-inspired fault-tolerant electronic architecture

Bremner¹,

Liu²,

Samie³

et al. 2013

Bioinspir. Biomim.

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As electronic devices become increasingly complex, ensuring their reliable, fault-free operation is becoming correspondingly more challenging. It can be observed that, in spite of their complexity, biological systems are highly reliable and fault tolerant. Hence, we are motivated to take inspiration for biological systems in the design of electronic ones. In SABRE (self-healing cellular architectures for biologically inspired highly reliable electronic systems), we have designed a bio-inspired fault-tolerant hierarchical architecture for this purpose. As in biology, the foundation for the whole system is cellular in nature, with each cell able to detect faults in its operation and trigger intra-cellular or extra-cellular repair as required. At the next level in the hierarchy, arrays of cells are configured and controlled as function units in a transport triggered architecture (TTA), which is able to perform partial-dynamic reconfiguration to rectify problems that cannot be solved at the cellular level. Each TTA is, in turn, part of a larger multi-processor system which employs coarser grain reconfiguration to tolerate faults that cause a processor to fail. In this paper, we describe the details of operation of each layer of the SABRE hierarchy, and how these layers interact to provide a high systemic level of fault tolerance.

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Section: Methods For Fault Detection In the Test And Repair Systemsmentioning

confidence: 99%