The paper presents a simulation-based test algorithm generation and test scheduling methodology for multi-port memories. The purpose is to minimize the testing time while keeping the test algorithm in a simple and regular format for easy test generation, fault diagnosis, and built-in self-test (BIST) circuit implementation. Conventional functional fault models are used to generate tests covering most defects. In addition, multi-port specific defects are covered using structural fault models. Port-scheduling is introduced to take advantage of the inherent parallelism among different ports. Experimental results for commonly used multi-port memories, including dual-port, four-port, and n-read-1-write memories, have been obtained, showing that efficient test algorithms can be generated and scheduled to meet different test bandwidth constraints. Moreover, memories with more ports benefit more with respect to testing time.

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Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experiences of the FA engineer is time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new developmentjow that enables the product to reach a profitable yield level as soon as possible. Demand in methodologies that allow FA automation thus increases rapidly in recent years. This paper proposes a systematic diagnosis approach based on failure patterns and functional fault models of semiconductor memories. By circuit-level simulation and analysis, we have also developed a fault pattern generator. Defect diagnosis and FA can be performed automatically by using the fault patterns, reducing the time in yield improvement. The main contribution of the paper is thus a methodology and procedure for accelerating FA and yield optimization for semiconductor memories.

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