Fault pattern oriented defect diagnosis for memories

Abstract

Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experiences of the FA engineer is time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new developmentjow that enables the product to reach a profitable yield level as soon as possible. Demand in methodologies that allow FA automation thus increases rapidly in recent years. This paper proposes a systematic diagnosis approach based on failure patterns and functional fault models of semiconductor memories. By circuit-level simulation and analysis, we have also developed a fault pattern generator. Defect diagnosis and FA can be performed automatically by using the fault patterns, reducing the time in yield improvement. The main contribution of the paper is thus a methodology and procedure for accelerating FA and yield optimization for semiconductor memories.

Hierarchical Memory Diagnosis

“…Memory diagnosis approaches use various methods to identify and diagnose memory faults, e.g., fault pattern identification [6][7][8], fault signatures [1,9,10]. However, they hardly make any distinction between memory array faults and faults in other parts of the memory, such as decoders and peripherals.…”