Embedded memory fail analysis for production yield enhancement

Baltagi, Y.; Rosi, Daniele Li; Tancorre, V.; Garagnon, Christophe; Faehn, Eric; Barone, M.; Appello, D.; Suzor, Christophe

doi:10.1109/asmc.2011.5898161

Cited by 7 publications

(3 citation statements)

References 5 publications

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“…READ/WRITE assist function and internal self-timing control function are generally embedded on nanoscale SRAM to enhance SRAM operation margin especially for the lower voltage operation as shown in Fig. 1 [5]. Assist and timing circuits adjust powers and internal CLK speed associated with SRAM operation to achieve low voltage operation.…”

Section: Electrical Stress Test Methodologymentioning

confidence: 99%

Advanced Soft Defect Screen Methodology for Nanoscale SRAM Yield Improvement

Kim

2021

International Symposium for Testing and Failure Analysis

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As technology scales down, the density of Static Random Access Memory (SRAM) devices increases drastically, and their storage capacity grows at the same time. Moreover, SRAMs become more prone to physical defects in each technology node. In addition, resistive defects and parametric defects are increasing which are hard to detect by the conventional test. Thus, the need of effective tests with high fault coverage and low cost increases. In this work, we study the reuse of assist technique (read and write assist) and timing margin control technique, commonly applied to improve the functional margins of SRAM core-cells, to improve the coverage of hard-to-detect marginal defects. This analysis is based on extensive injection of resistive bridging defects in core-cells of a commercial low-power SRAM. We show that assist circuits and timing control circuits can be leveraged to increase the defect coverage can be increases up to 28% at nominal operation voltage by simulation. Some successful case studies are also discussed to demonstrate the efficiency of the proposed electrical stress test methodology.

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Section: Electrical Stress Test Methodologymentioning

confidence: 99%

Advanced Soft Defect Screen Methodology for Nanoscale SRAM Yield Improvement

Kim

2021

International Symposium for Testing and Failure Analysis

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“…Oftentimes a given bitmap pattern will usually have the same underlying defect mechanism. Thus a Pareto of bitmap patterns will be roughly equivalent to a Pareto of silicon defects [8]. Such information can be very useful to understand the memory manufacturing yield.…”

Section: Introductionmentioning

confidence: 99%

A Hybrid Flow for Memory Failure Bitmap Classification

Huang

Cheng

et al. 2012

2012 IEEE 21st Asian Test Symposium

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Failure bitmaps of manufactured memory arrays may contain the information of some systematic defects and have hence been used to monitor the process and to improve the memory yield. It is important to have an accurate flow to classify the memory failure bitmap signatures. The memory bitmap signature classification can be either dictionary based or machine learning based. This paper introduces a hybrid flow that can combine dictionary based and machine learning based methods. The proposed method can enhance the accuracy of signature classification, and more importantly, it has the capability of learning new memory bitmap signatures unseen before.

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“…For this sake, SRAM is often chosen to be the process qualification vehicle during technology development or yield learning vehicle during product manufacturing. Consequently, Failure Analysis (FA) of SRAM is crucial for the process improvement and yield learning of a new process technology learning and development [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

Kim

et al. 2021

International Symposium for Testing and Failure Analysis

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Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

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Embedded memory fail analysis for production yield enhancement

Cited by 7 publications

References 5 publications

Advanced Soft Defect Screen Methodology for Nanoscale SRAM Yield Improvement

Advanced Soft Defect Screen Methodology for Nanoscale SRAM Yield Improvement

A Hybrid Flow for Memory Failure Bitmap Classification

SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

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