A System-layer Infrastructure for SoC Diagnosis

Bernardi, P.; Grosso, M.; Rebaudengo, Maurizio; Reorda, M. Sonza

doi:10.1007/s10836-007-5014-6

Cited by 2 publications

(2 citation statements)

References 31 publications

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“…Roughly speaking, in all the cited cases the execution of diagnostic procedures consists in reiterated test accesses to those cores identified as faulty during the test screening and stems from the basic test procedure [3]. In fact, each access to a faulty core is a slightly modified test procedure.…”

Section: Design-for-test and Diagnosis Of Socsmentioning

confidence: 99%

“…The preservation of the original fault coverage is guaranteed by the fact that the union of all the slices is the original pattern set; at the same time, an improved diagnostic resolution can be obtained since at least one signature is read during every smaller test execution. As the reader would expect, the employed BIST architecture has to own programmability features allowing to implement test customization [3]; a minor drawback is that the required diagnostic time could be greatly larger than the test time.…”

Section: Figure 1: Transformation Of a Logic Bist Test Procedures Intomentioning

confidence: 99%

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An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs

Appello

Bernardi

Cagliesi³

et al. 2008

2008 13th European Test Symposium

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This paper describes a novel approach to enhance the process of reliability characterization for VLSI SoC products. To do this, we exploit Design for Test and Diagnosis structures in combination with new low-cost tester features and architecture. The main focus of our work is to obtain a modeling of the degradation of selected parameters measurable through at-speed testing.The paper reviews the current approach for reliability characterization and shows the achieved enhancement on efficiency and effectiveness. Results shown are related to experiments run on a vehicle released on a 90nm technology.

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Section: Design-for-test and Diagnosis Of Socsmentioning

confidence: 99%

Section: Figure 1: Transformation Of a Logic Bist Test Procedures Intomentioning

confidence: 99%