A Barrier Controlled Charge Plasma-Based TFET With Gate Engineering for Ambipolar Suppression and RF/Linearity Performance Improvement

Nigam, Kaushal; Pandey, S. K.; Kondekar, P. N.; Sharma, Dheeraj; Parte, Pawan Kumar

doi:10.1109/ted.2017.2693679

Cited by 71 publications

(29 citation statements)

References 23 publications

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“…Considering the exponential decrease of the tunneling rate with the tunnel distance [ 25 ], the BTBT process from source to channel is assumed to be extended up to the channel center and the BTBT process from channel to drain usually known as the ambipolar effect [ 26 ] is limited in the right part of the channel. Thus the tunnel current can be described by Equation (14).…”

Section: Model Derivation For Inas/si Hsp-tfetmentioning

confidence: 99%

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Zhang

et al. 2019

Nanomaterials

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The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.

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Section: Model Derivation For Inas/si Hsp-tfetmentioning

confidence: 99%

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Zhang

et al. 2019

Nanomaterials

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“…5 a indicates the transition in f T with respect to gate voltage for both the devices. It can be observed that f T increases at higher gate voltages as transconductance increases with respect to gate voltage at higher gate voltages [32].…”

Section: Resultsmentioning

confidence: 99%

Performance investigation of asymmetric double‐gate doping less tunnel FET with Si/Ge heterojunction

Sharma

Kaur

2020

IET Circuits, Devices & Systems

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Tunnel field effect transistors (TFETs) have been exhibiting an enticing performance to succeed in metal-oxidesemiconductor technology. However, TFET also possesses several challenges such as low drive current, ambipolarity, and requirement of abrupt doping profiles for the occurrence of band-to-band tunnelling (BTBT) conduction mechanism at the junction. To overcome these challenges, the authors propose a heterojunction doping less tunnel field-effect transistor with an asymmetric double gate (HJ ADG DLTFET). This device employs a low bandgap material at the source region, which increases the BTBT rate at the channel-source interface leading to enhanced drive current while maintaining low off-current. Consequently, an increment of one order for I ON (∼1.5 × 10 −5 A/µm) compared to the conventional ADG DLTFET has been provided by this device. Additionally, the comparative analysis of the proposed device and conventional one has been performed to reveal the advantages of the proposed structure in terms of transfer characteristics, transconductance, gate-todrain capacitance, cutoff frequency, gain-bandwidth product, device efficiency, and transconductance frequency product. Moreover, the effect of gate length and drain voltage variations has been analysed for HJ ADG DLTFET concerning the aforementioned characteristics.

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“…All the simulations are carried out by using SILVACO 2D‐ATLAS TCAD [21]. Numerous inbuilt models are used by simulator; in [22, 23] basic model and mechanism of TFET is BTBT model. BTBT calculates the generation rate throughout the meshing points of the structure.…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

Approach to suppress ambipolarity and improve RF and linearity performances on ED‐Tunnel FET

Chandan

Dasari

Yadav

et al. 2018

Micro & Nano Letters

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This work reports a dual metal bipolar gate-based electrically doped tunnel field-effect transistor (DMBG-ED-TFET) which overcomes the ambipolarity issue and gives improved radio frequency (RF) and linearity metrics. The formations of n + , p + drain and source regions in this device is performed by applying polarity biases at polarity gate (PG)-1 and PG-2 with 1.2 and −1.2 V. In DMBG-ED-TFET, the gate is alienated into three subdivisions and each subdivision named as tunnel gate (M1), BG (M2) and auxiliary gate (M3) with their respective work functions as f M1 , f M2 and f M3 , respectively. Finally, some existent applications were applied on a proposed device with different possible combinations (work function). Those different possible combinations of work function, the proposed device (DMBG-ED-TFET) gives superior results with f M1 = f M3 , f M2 , where f M1 is near to source region because to increase the I on current and f M3 is located near the drain region to overwhelm the ambipolarity. Additionally, the application of work function engineering on the proposed device results in improving the DC characteristics along with analogue/RF and linearity figure of merits (VIP3, IIP3 and IMD3) also discussed.

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A Barrier Controlled Charge Plasma-Based TFET With Gate Engineering for Ambipolar Suppression and RF/Linearity Performance Improvement

Cited by 71 publications

References 23 publications

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Performance investigation of asymmetric double‐gate doping less tunnel FET with Si/Ge heterojunction

Approach to suppress ambipolarity and improve RF and linearity performances on ED‐Tunnel FET

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