A 90 nm CMOS &lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;$+$&lt;/tex&gt;&lt;/formula&gt;11 dBm IIP3 4 mW Dual-Band LNA for Cellular Handsets

Fatin, Gholamreza Zare; Koozehkanani, Ziaddin Daie; Sjöland, Henrik

doi:10.1109/lmwc.2010.2055839

Cited by 14 publications

(4 citation statements)

References 6 publications

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“…FoM I is calculated by considering the gain, frequency, NF, DC power consumption, and the normalized input impedance (33). This lagging is due to the differential structure used in Fatin et al, 14 which is designed for highlinearity requirements. IIP3 is required to be greater than −10 dBm for the LNAs of mobile communication.…”

Section: Results and Analysismentioning

confidence: 99%

“…The voltage gain (A v1 ) of the CG amplifier is derived as in Equation (13), and it is tuned to the 0.9 GHz of frequency. These parasitic capacitances are increasing and decreasing the e 1 and A v1 , respectively (14). The gain is increased by g m1 and Z 01 , and it is reduced by e 1 .…”

Section: Gain Calculationmentioning

confidence: 95%

“…The device dimensions are increased to increase the g m1 , but C gs1 and C gd1 also get increased. These parasitic capacitances are increasing and decreasing the e 1 and A v1 , respectively (14).…”

Section: Gain Calculationmentioning

confidence: 97%

“…In FoM II calculation, reference 14 secures the first place, and the proposed design comes next. This lagging is due to the differential structure used in Fatin et al, 14 which is designed for highlinearity requirements.…”

Section: Figure 11mentioning

confidence: 99%

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Design and analysis of 0.9 and 2.3‐GHz concurrent dual‐band CMOS LNA for mobile communication

Roobert¹,

Rani²

2019

Circuit Theory & Apps

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A complementary metal-oxide-semiconductor (CMOS) dual-band low-noise amplifier (LNA) for 2G/3G/4G mobile communications is presented. It operates at 0.9 and 2.3 GHz of frequencies. The dual-band operation is achieved by adding a modified notch-filtering path in the wideband LNA. The modified notch-filtering path does not require additional power to cancel the signals of the stop band frequency. The impact of the filtering path in the proposed LNA is analyzed. Improved results are observed in dual bands of frequency. Sustainability of the LNA under process corner variation and temperature variation are examined, and it is found to be suitable for the application. The proposed LNA is designed at 90-nm technology in Cadence Virtuoso with 0.5 and 0.6-V supply. The post-layout simulation shows 22 dB of gain (S 21 ), 2 dB of Noise Figure (NF), and −5.5 dBm of IIP3 at the high band. In the low band, 24 dB of S 21 , 2.7 dB of NF, and −6.65 dBm of IIP3 are reached. The circuit consumes 5.2 mW of power and 0.0918 mm 2 of area. The efficiency of the LNA is estimated by the figure of merit, and comparable results are secured in the proposed work.

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Section: Results and Analysismentioning

confidence: 99%

Section: Gain Calculationmentioning

confidence: 95%

Section: Gain Calculationmentioning

confidence: 97%

Section: Figure 11mentioning

confidence: 99%

See 2 more Smart Citations

Design and analysis of 0.9 and 2.3‐GHz concurrent dual‐band CMOS LNA for mobile communication

Roobert¹,

Rani²

2019

Circuit Theory & Apps

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Design of a reconfigurable front‐end for a multistandard receiver for the frequency range of 800 MHz to 2.5 GHz

Fatin

Koozehkanani

Fotowat-Ahmady

et al. 2018

Circuit Theory & Apps

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In this paper, a reconfigurable receiver front-end for the frequency range of 800 MHz to 2.5 GHz is presented. The radio frequency front-end is realized in wideband form with reconfigurable baseband filter. The proposed frontend targets the GSM, WLAN, WCDMA, and GPS standards residing in the aimed frequency range. The necessary specifications for each individual standard have been revisited and recalculated. The interaction of the different standards and their interoperability has been thoroughly investigated and extra specifications derived for the multistandard receiver. The multistandard receiver has been designed, layouted, and simulated in RFCMOS 0.18-μm process.

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A Dual-Wideband CMOS LNA Using Gain–Bandwidth Product Optimization Technique

Chen

Wang

2016

Circuits Syst Signal Process

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A 90 nm CMOS <formula formulatype="inline"> <tex Notation="TeX">$+$</tex></formula>11 dBm IIP3 4 mW Dual-Band LNA for Cellular Handsets

Cited by 14 publications

References 6 publications

Design and analysis of 0.9 and 2.3‐GHz concurrent dual‐band CMOS LNA for mobile communication

Design and analysis of 0.9 and 2.3‐GHz concurrent dual‐band CMOS LNA for mobile communication

Design of a reconfigurable front‐end for a multistandard receiver for the frequency range of 800 MHz to 2.5 GHz

A Dual-Wideband CMOS LNA Using Gain–Bandwidth Product Optimization Technique

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