A Dual-Wideband CMOS LNA Using Gain–Bandwidth Product Optimization Technique

Chen, Chun‐Chieh; Wang, Yen‐Chun

doi:10.1007/s00034-016-0322-7

Cited by 8 publications

(4 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The LNA was designed for 5.5 GHz frequency. Chun-Chieh Chen et al [28] have presented gain and product optimization technique for increasing gain in LNA. The design was presented cascode LNA, common gate and dual bandwidth that decreasing value of capacitance in equivalent with the consideration the resonator loads.…”

Section: Optimization Based Control Techniquesmentioning

confidence: 99%

An Extensive Review On: Low Noise Amplifier for Millimeter and Radio Frequency Waves

2021

View full text Add to dashboard Cite

In today’s world, radio receiver system is a prevailing wireless technology in that the major part is Low Noise Amplifier (LNA) which widely used to improve weak signals in many applications with millimeter and radio frequency waves such as optical communication, multimode transceivers and measurement instrumentations. The real drawbacks of LNA is that it fails to maintain specific properties in critical conditions like as minimum power consumption, provide low noise figure, input matching and linearity. Additionally, promoted by various application demands, design methods and control methods must require to improve performance of LNA. The performance of LNA can be improved by adding extra components in basic circuit by proper arrangement for millimeter and radio frequency waves. The review paper provides information about design methodology, optimization techniques and control techniques. The different design of LNA is reviewed and analyzed such as 3-stage near-mm Wave LNA, 5-stage near-mm Wave LNA, common-gate amplifier, shunt-feedback amplifier, Resistor-terminated common-source amplifier, Traditional inductor-less amplifiers, cascode connection and double common source. This review paper also provides the information about design circuit diagram. The performance improvement of LNA can be achieved with the help of different techniques and our review based on optimization and control techniques with parameter tuning. Finally, the direction for the future study is presented based on review analysis of LNA.

show abstract

Section: Optimization Based Control Techniquesmentioning

confidence: 99%

An Extensive Review On: Low Noise Amplifier for Millimeter and Radio Frequency Waves

2021

View full text Add to dashboard Cite

show abstract

“…Z in1 is written by considering the input impedance of the CG transistor N 1 and the source inductance L 5 (8). As depicted in Figure 4, Z 3 and Z in1 are in series with each other, and these impedances are added to calculate Z 4 in (9).…”

Section: Impedance Calculationmentioning

confidence: 99%

“…Previous works with notch filtering structure require an additional biasing network, and the power consumption of the circuit gets increased. 9 In the proposed design, concurrent dual-band operation is achieved by a modified notch filtering technique. The signal blocking is implemented inside the amplifier loop, and the power consumption gets reduced.…”

mentioning

confidence: 99%

Design and analysis of 0.9 and 2.3‐GHz concurrent dual‐band CMOS LNA for mobile communication

Roobert¹,

Rani²

2019

Circuit Theory & Apps

View full text Add to dashboard Cite

A complementary metal-oxide-semiconductor (CMOS) dual-band low-noise amplifier (LNA) for 2G/3G/4G mobile communications is presented. It operates at 0.9 and 2.3 GHz of frequencies. The dual-band operation is achieved by adding a modified notch-filtering path in the wideband LNA. The modified notch-filtering path does not require additional power to cancel the signals of the stop band frequency. The impact of the filtering path in the proposed LNA is analyzed. Improved results are observed in dual bands of frequency. Sustainability of the LNA under process corner variation and temperature variation are examined, and it is found to be suitable for the application. The proposed LNA is designed at 90-nm technology in Cadence Virtuoso with 0.5 and 0.6-V supply. The post-layout simulation shows 22 dB of gain (S 21 ), 2 dB of Noise Figure (NF), and −5.5 dBm of IIP3 at the high band. In the low band, 24 dB of S 21 , 2.7 dB of NF, and −6.65 dBm of IIP3 are reached. The circuit consumes 5.2 mW of power and 0.0918 mm 2 of area. The efficiency of the LNA is estimated by the figure of merit, and comparable results are secured in the proposed work.

show abstract

“…inversely proportional to the equivalent loading capacitance 31 of the resonator [18]. Although C. C. Chen et al proposed 32 a gain-bandwidth product (GBW) optimization technique to 33 extend the bandwidth of the tuned amplifier, the linearity 34 weakens due to the dc bias near the triode region boundary 35 [6], [12]. Yu et al proposed a switched multi-tap transformer 36 utilized in the input matching network of an inductively 37 degenerated CS amplifier [13].…”

Section: Introductionmentioning

confidence: 99%

A 2.35/2.4/2.45/2.55 GHz Low-Noise Amplifier Design Using Body Self-Biasing Technique for ISM and LTE Band Application

Wang

Huang²,

Jin

2019

IEEE Access

Self Cite

View full text Add to dashboard Cite

This paper presents a quadruple-band low noise amplifier (LNA) which utilizes a differential pair common-source (CS) cascode amplifier to drive a LC-tank loading. The capacitors array are parallel with the LC-tank to implement the central frequency selection. The band-selection switch employs the binary voltage controlling to alter the equivalent capacitance of capacitors array of the loading LC-tank, which results in the central frequency of the LNA is switched. The body self-biasing technique is designed to minimize the noise contribution caused by the body effect of the MOS devices. In addition, the analysis of the transistors dimension ratio versus output referred 1-dB compression point (OP 1−dB ) is presented to describe the design of the linearity optimization in CS cascode LNA. The |S 21 | is 16.8, 16.63, 16.78, 16.39 dB at 2.35, 2.4, 2.45, 2.55 GHz, respectively. The noise figure (NF) is under 2.75 dB between the quadrupleband mode. This proposed LNA is simulated by 55 nm RF CMOS process and consumes 3.75 mW excluding output buffer from 1.25 V supply.

show abstract

A Dual-Wideband CMOS LNA Using Gain–Bandwidth Product Optimization Technique

Cited by 8 publications

References 18 publications

An Extensive Review On: Low Noise Amplifier for Millimeter and Radio Frequency Waves

An Extensive Review On: Low Noise Amplifier for Millimeter and Radio Frequency Waves

Design and analysis of 0.9 and 2.3‐GHz concurrent dual‐band CMOS LNA for mobile communication

A 2.35/2.4/2.45/2.55 GHz Low-Noise Amplifier Design Using Body Self-Biasing Technique for ISM and LTE Band Application

Contact Info

Product

Resources

About