Design and analysis of 0.9 and 2.3‐GHz concurrent dual‐band CMOS LNA for mobile communication

Roobert, A. Andrew; Rani, D. Gracia Nirmala

doi:10.1002/cta.2688

Cited by 13 publications

(7 citation statements)

References 19 publications

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“…where f 1 and f 2 represent the centre frequencies of the low band and the high band of the concurrent DB-LNA, respectively. According to Table 4, the DB-LNA in (Roobert & Rani [25]) presents a high power gain and low NF at both bands. However, its operating frequencies are lower than those of the proposed DB-LNA.…”

Section: Simulation Resultsmentioning

confidence: 99%

Concurrent Dual-Band Inverter-Based Low Noise Amplifier (LNA) for WLAN Applications

2021

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In this paper, a two-stage concurrent dual-band low noise amplifier (DB-LNA) operating at 2.4/5.2-GHz is presented for Wireless Local Area Network (WLAN) applications. The current-reused structure using resistive shunt-shunt feedback is employed to reduce power dissipation and achieve a wide frequency band from low frequency to-5.5-GHz in the inverter-based LNA. The second inverter-based stage is employed to increase the gain and obtain a flat gain over the frequency band. An LC network is also inserted at the proposed circuit output to shape the dual-band frequency response. The proposed concurrent DB-LNA is designed for RF-TSMC 0.18-μm CMOS technology, which consumes 10.8 mW from a power supply of 1.5 V. The simulation results show that the proposed DB-LNA achieves a direct power gain (S 21) of 13.7/14.1 dB, a noise figure (NF) of 4.2/4.6 dB, and an input return loss (S 11) of −12.9/−14.6 dBm at the 2.4/5.2-GHz bands.

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Section: Simulation Resultsmentioning

confidence: 99%

Concurrent Dual-Band Inverter-Based Low Noise Amplifier (LNA) for WLAN Applications

2021

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“…10,11 High gain is required to effectively amplify a weak signal, and low gain is required for the strong signal to avoid the saturation of LNA. 12 Thus, the variable gain can improve the sensitivity of the LNA. In high frequency applications like 5G mobile communication, the signal strength varies within a short distance.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of 28 GHz CMOS low power LNA with 6.4 dB gain variability for 5G applications

Roobert¹,

Arunodhayamary²,

Rani³

et al. 2022

Trans Emerging Tel Tech

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A 28 GHz two stage low noise amplifier (LNA) is proposed with envelope detection technique for power reduction (21.62%) and tunable negative feedback capacitor for gain variation in 40 nm CMOS technology. The envelope detection circuit turn‐on the second half of the LNA by the RF signal input received at the first stage. The default gain is increased (31.53%) by the tunable negative feedback capacitor circuit of the LNA with the control voltage from 0 to 1 V. In addition, 6.22 GHz of bandwidth is achieved with the tunable gain from 20.3 dB to 26.7 dB. The first stage of the LNA is designed with the inductive source degeneration for the noise reduction, and the multiple‐gate topology is involved in the second stage to improve the linearity. The third‐order input intercept point and the noise figure of the LNA are −7 dBm and 2.86 dB, respectively. When the second stage is turned‐on and turned‐off the LNA consumes 7.4 mW and 5.8 mW of power, respectively, from the 1 V supply. The proposed LNA requires 0.19 mm2 of core area. The performance of the LNA under process corner variation and temperature variation are analyzed.

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“…So to solve this problem, different topologies are presented for wideband CMOS LNAs. [2][3][4][5][6] Commendable features of distributed amplifiers are wideband impedance matching and wideband gain. However, they have high power dissipation and large circuit area.…”

Section: Introductionmentioning

confidence: 99%

Analysis and design of ultra‐wideband low noise amplifier using complementary structure with series inductive peaking technique and shunt feedback

Kazemi

Hayati

2021

Circuit Theory & Apps

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In this paper, an ultra-wideband low noise amplifier (LNA) is presented using 0.18-μm RF CMOS technology. A complementary structure with series inductive peaking technique is introduced by using two inductor-loops to achieve flat gain. In the first and third stages, two complementary structures are utilized to achieve a high and flat gain, a wideband input impedance matching and a low noise figure. In addition, a shunt feedback is utilized to increase input impedance matching and stability. In the second stage, a common source structure is used as interstage, which increases the À3 dB bandwidth. The designed LNA presents a high and flat gain of 15.6-16.5 dB, an excellent input return loss better than À11 dB and a good NF of 2.2-3 dB in the frequency range of 3.1-10.6 GHz. Also, the proposed structure consumes 6.8 mW from a 0.8-V supply voltage and has an IIP3 of À4 dBm at 6.5 GHz. The proposed structure only occupies 0.59 mm 2 .

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Design and analysis of 0.9 and 2.3‐GHz concurrent dual‐band CMOS LNA for mobile communication

Cited by 13 publications

References 19 publications

Concurrent Dual-Band Inverter-Based Low Noise Amplifier (LNA) for WLAN Applications

Concurrent Dual-Band Inverter-Based Low Noise Amplifier (LNA) for WLAN Applications

Design and analysis of 28 GHz CMOS low power LNA with 6.4 dB gain variability for 5G applications

Analysis and design of ultra‐wideband low noise amplifier using complementary structure with series inductive peaking technique and shunt feedback

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