Design of a reconfigurable front‐end for a multistandard receiver for the frequency range of 800 MHz to 2.5 GHz

Fatin, Gholamreza Zare; Koozehkanani, Ziaddin Daie; Fotowat-Ahmady, Ali; Sobhi, Jafar; Farrell, Alison

doi:10.1002/cta.2476

Cited by 3 publications

(4 citation statements)

References 27 publications

(41 reference statements)

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“…The performance of the front‐end blocks utilized in the Verilog‐AMS model is derived from the know how of the previous implementation . Moreover, all the other implementations do not include the capability to identify the incoming RF signal standard. The implementation can estimate the standard but lack the capability to change the received standard dynamically.…”

Section: Performance Results and Discussionmentioning

confidence: 99%

“…The existing reconfigurable receivers in the literature are reported as wideband sampling receivers and multistandard subsampling receivers . In these sampling receivers, selection of the sampling frequency defines the receiver architecture, which includes an oversampling receiver with discrete‐time mixer (DTM), time‐interleaved (TI) discrete‐time oversampling receiver, and sub‐sampling receiver .…”

Section: Introductionmentioning

confidence: 99%

“…The existing reconfigurable receivers in the literature are reported as wideband sampling receivers [5][6][7][8] and multistandard subsampling receivers. [9][10][11][12][13][14] In these sampling receivers, selection of the sampling frequency defines the receiver architecture, which includes an oversampling receiver with discrete-time mixer (DTM), 5 time-interleaved (TI) discrete-time oversampling receiver, 6 and sub-sampling receiver. 7 The architecture in the study of Barrak et al 9 utilizes two-stage subsampling based down-conversion along with the tuned filters at each stage to improve the overall performance.…”

Section: Introductionmentioning

confidence: 99%

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A −40‐dB EVM 20‐MHz subsampling multistandard receiver architecture with dynamic carrier detection, bandwidth estimation, and EVM optimization

Kale

Sturm

Pasupureddi

2019

Circuit Theory & Apps

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Summary In this work, a reconfigurable multistandard subsampling receiver with dynamic carrier frequency detection and system‐level EVM optimizations is proposed. Ideal software defined radio (SDR) receivers promise complete flexibility at the expense of high‐performance analog‐to‐digital converters (ADCs) that are challenging to implement in current technologies for low‐power applications. This scenario leads to the research of digital intensive sampling receivers with discrete‐time signal processing (DTSP) implemented in analog domain. This approach makes it feasible to move channel selection filtering and dynamic gain adaptability from analog to digital domain. The proposed receiver employs subsampling down‐conversion along with subband filters to dynamically detect the carrier frequency of the incoming signal, estimate its bandwidth, and identify if the signal is present in one of the target standard bands. This carrier detection provides a unique capability to reconfigure the receiver dynamically. Additionally, in this work, system‐level EVM optimization is proposed considering frequency synthesizer phase noise, IQ mismatch, sampling frequency selection and block‐level gain, noise, and nonlinearity. The RF front end of the proposed receiver is modeled in Verilog‐AMS whereas the digital signal processing is implemented in Simulink‐Matlab. The complete receiver has been verified to detect and process three different bands belonging to three different standards (GSM, UMTS, and WLAN) with the carrier frequency ranging from 0.9 to 2.5 GHz. Test signals with 4‐QAM modulation, maximum bandwidth of 20 MHz, and input‐dynamic range from –109 to –20 dBm is utilized to demonstrate the receiver performance including an EVM of –40 dB.

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Section: Performance Results and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A −40‐dB EVM 20‐MHz subsampling multistandard receiver architecture with dynamic carrier detection, bandwidth estimation, and EVM optimization

Kale

Sturm

Pasupureddi

2019

Circuit Theory & Apps

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“…The progress of wireless communications has motivated a strong interest towards the development of multistandard receivers [1][2][3]. Significant research efforts have been dedicated in developing wideband receivers, which are compactness, power, and cost-efficient compared with multiple narrowband front-ends.…”

Section: Introductionmentioning

confidence: 99%

A wideband balun‐LNA employing symmetrical CCC technique and balanced outputs

Eskandari

Ebrahimi

Baghtash

2021

IET Circuits, Devices & Syst

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The conventional active CG‐CS balun low‐noise amplifiers (LNAs) with asymmetric outputs exploit a relatively weak output balance, limited IIP2, and high power consumption. This study presents a wideband balun‐LNA with symmetrical outputs. The proposed LNA utilizes a symmetrical capacitive cross‐coupled (CCC) technique between active balun and resistor loads to achieve wideband output balancing, thereby enhancing the gain and linearity performance. In addition, double noise reduction techniques are exploited to implement symmetrical outputs, reduce power consumption, and avoid noise figure (NF) degradation. First, the common‐source (CS) stage in parallel with the common‐gate (CG) amplifier nullifies the noise of the CG transistor. Second, an Aux amplifier in the CS stage reduces the noise of the CS transistor and avoids scaling up the CS transistor with respect to the CG transistor. The proposed LNA is implemented in 0.18 μm complementary metal‐oxide semiconductor technology, and its performance is evaluated through spectre post‐layout simulations. The proposed LNA exhibits a voltage gain of 25.4 dB and an NF of 3.2–3.8 dB over 3 GHz operating bandwidth ranging from 1 to 4 GHz. The IIP3 and IIP2 are achieved as ‐1.66 dBm and +28.97 dBm, respectively. The proposed structure consumes 5.5 mW from 1.5V power supply and occupies an active area of 0.29 mm2.

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