A wideband balun‐LNA employing symmetrical CCC technique and balanced outputs

Abstract

The conventional active CG‐CS balun low‐noise amplifiers (LNAs) with asymmetric outputs exploit a relatively weak output balance, limited IIP2, and high power consumption. This study presents a wideband balun‐LNA with symmetrical outputs. The proposed LNA utilizes a symmetrical capacitive cross‐coupled (CCC) technique between active balun and resistor loads to achieve wideband output balancing, thereby enhancing the gain and linearity performance. In addition, double noise reduction techniques are exploited to implement symmetrical outputs, reduce power consumption, and avoid noise figure (NF) degradation. First, the common‐source (CS) stage in parallel with the common‐gate (CG) amplifier nullifies the noise of the CG transistor. Second, an Aux amplifier in the CS stage reduces the noise of the CS transistor and avoids scaling up the CS transistor with respect to the CG transistor. The proposed LNA is implemented in 0.18 μm complementary metal‐oxide semiconductor technology, and its performance is evaluated through spectre post‐layout simulations. The proposed LNA exhibits a voltage gain of 25.4 dB and an NF of 3.2–3.8 dB over 3 GHz operating bandwidth ranging from 1 to 4 GHz. The IIP3 and IIP2 are achieved as ‐1.66 dBm and +28.97 dBm, respectively. The proposed structure consumes 5.5 mW from 1.5V power supply and occupies an active area of 0.29 mm2.

A PVT resilient true‐time delay cell

“…where $${g}_{m3,{M}_{5}}$$ and $${g}_{m3,{M}_{4}}$$ have positive amounts, but A 1 is negative [27]. So, in a good bias range, the g m 3 of both transistors cancel each other.…”