A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump

Abstract

In this paper, a low jitter 16-phases delay locked loop (DLL) is proposed based on a simple and sensitive phase detector (PD). Dead-zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modi¯ed to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched di®erential pairs. Duty cycle of output di®erential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results con¯rm that DLL loop can provide 16-phases in frequency range of 80 to 410 MHz, consuming total power of 3.5 and 5.6 mW, respectively. The dead-zone of PD is also reduced from 80 to 14 ps when the pulse generator section is eliminated. Also, RMS jitter of about 45 and 1.76 ps are obtained at 80 and 410 MHz, respectively, when the supply voltage is subject to around 40 mV peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05 mm 2 active area in a 0.18 m CMOS technology.

A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor

“…The analog DLL consist of phase detector (PD), charge pump (CP), loop filter (LF) and voltage controlled delay line (VCDL) [9]. The architecture proposed in [10] offers better jitter performance and VCDL provides acceptable power supply rejection ratio (PSRR). However analog DLL suffers from high power consumption, long lock time and large area due to LF.…”