Low-Power High-Frequency Phase Frequency Detector for Minimal Blind-Zone Phase-Locked Loops

Sofimowloodi, Sobhan; Razaghian, Farhad; Gholami, Mohammad

doi:10.1007/s00034-018-0887-4

Cited by 29 publications

(6 citation statements)

References 10 publications

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“…PFDs are always active in a PLL system, due to which consumption of power in the PFD is high [10]. Therefore, there is a need to design PFDs to minimize the power consumption and thus when integrated with the PLL, reduces the power consumption of PLL.…”

Section: Implementation Of Phase/frequency Detectormentioning

confidence: 99%

Design and Implementation of Phase Frequency Detectors for Low-Power PLL

Bharadwaj¹,

Parashar²,

Dhanush³

et al. 2021

Lecture Notes in Electrical Engineering

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Section: Implementation Of Phase/frequency Detectormentioning

confidence: 99%

Design and Implementation of Phase Frequency Detectors for Low-Power PLL

Bharadwaj¹,

Parashar²,

Dhanush³

et al. 2021

Lecture Notes in Electrical Engineering

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“…For the purpose of avoiding the above problems of the traditional structure, a phase detector with a completely symmetrical structure is used [ 22 ], as shown in Figure 6 a. It can function well in [−

] with no dead zone and the effective electrical level of the output signal is low-level.…”

Section: Proposed Addll Structurementioning

confidence: 99%

A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC

Tong

Wang

Zhang

et al. 2021

Sensors

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This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources. In order to effectively solve the dithering phenomenon after locking, a replica delay line and a modified binary search algorithm with two modes were introduced in our ADDLL, which can significantly reduce the peak-to-peak jitter of the replica delay line. In addition, digital codes for a replica delay line can be conveniently applied to the delay line of multi-channel Vernier TDC while maintaining consistency between channels. The proposed ADDLL has been designed in 55 nm CMOS technology. In addition, the post-layout simulation results show that when operated at 1.2 V, the proposed ADDLL locks within 37 cycles and has a closed-loop characteristic, the peak-to-peak and root-mean-square jitter at 800 MHz are 6.5 ps and 1.18 ps, respectively. The active area is 0.024 mm2 and the power consumption at 800 MHz is 6.92 mW. In order to verify the performance of the proposed ADDLL, an architecture of dual ADDLL is applied to Vernier TDC to stabilize the Vernier delay lines against the process, voltage, and temperature (PVT) variations. With a 600 MHz operating frequency, the TDC achieves a 10.7 ps resolution, and the proposed ADDLL can keep the resolution stable even if PVT varies.

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“…In the subsequent year, Gholami [16] further modified the conventional PFD, which was able to achieve satisfactory operation frequency, however, the power consumption still remained very high. In 2019, Sofimowloodi [17] designed a symmetric PFD with relatively high operational frequency and low power consumption, but it was not still satisfactory in terms of operational frequency and power consumption. In this study, we have used cadence virtuoso as a computational tool to study the effect of varying MOSFET width, to obtain high operational frequency in a PFD topology, which is a key component in frequency synthesisers.…”

Section: Introductionmentioning

confidence: 99%

Optimisation and Performance Computation of a Phase Frequency Detector Module for IoT Devices

Hemel,

Reaz,

Ali

et al. 2024

AETiC

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The Internet of Things (IoT) is pivotal in transforming the way we live and interact with our surroundings. To cope with the advancement in technologies, it is vital to acquire accuracy with the speed. A phase frequency detector (PFD) is a critical device to regulate and provide accurate frequency in IoT devices. Designing a PFD poses challenges in achieving precise phase detection, minimising dead zones, optimising power consumption, and ensuring robust performance across various operational frequencies, necessitating complex engineering and innovative solutions. This study delves into optimising a PFD circuit, designed using 90 nm standard CMOS technology, aiming to achieve superior operational frequencies. An efficient and high-frequency PFD design is crafted and analysed using cadence virtuoso. The study focused on investigating the impact of optimising PFD design. With the optimised PFD, an operational frequency of 5 GHz has been achieved, along with a power consumption of only 29 µW. The dead zone of the PFD was only 25 ps.

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Low-Power High-Frequency Phase Frequency Detector for Minimal Blind-Zone Phase-Locked Loops

Cited by 29 publications

References 10 publications

Design and Implementation of Phase Frequency Detectors for Low-Power PLL

Design and Implementation of Phase Frequency Detectors for Low-Power PLL

A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC

Optimisation and Performance Computation of a Phase Frequency Detector Module for IoT Devices

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