A 50-mW/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface With Digital Eye-Tracking

Miki, Y.; Saito, Tatsuya; Yamashita, Hiroyuki; Yuki, Fumio; Baba, T.; Kôyama, Akio; Sonehara, M.

doi:10.1109/jssc.2004.824704

Cited by 32 publications

(22 citation statements)

References 9 publications

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“…The above techniques are discussed from the angle of the phase relationship adjustment. According to the synchronization relationship between clocks used to sample data locally and clocks used to generate data at transmitters, the clocking strategies can also be classified into (1) system or global clocking [4,6,11], where the reference clock is shared by both sides; (2) source synchronous/forwarded clocking [3,9,10,12,13], where a clock is fed from transmitters along data channels; (3) embedded clocking [7,8,22], where a clock is embedded into data at the transmitter, and then is extracted at the receiver; (4) local clocking [20,21,[24][25][26][27][28][29][30][31][32][33][34], where clocks are synthesized locally. (1) ~ (3) belong to synchronous, or mesochronous clocking strategies, which is applicable to applications A ~ C, and almost all of conventional CDR (clock and data recovery) techniques can be used; whereas (4) belongs to plesiochronous one, which is preferable to application C, and PI/PS (phase interpolation/ phase selection) type and blind-oversampling (blindoversampling) techniques are usually used [2,35].…”

Section: Conventional Clocking Strategiesmentioning

confidence: 99%

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

Zhang¹,

Li²,

Wang³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Two novel clocking strategies for a highspeed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard 0.18 µm CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.

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Section: Conventional Clocking Strategiesmentioning

confidence: 99%

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

Zhang¹,

Li²,

Wang³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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“…Multi-channel data transceivers offer a very good solution for increasing the total data communication speed [1]- [4]. Meanwhile, using optical links can help more to prepare a reliable and high speed environment for data transmission [5].…”

Section: Introductionmentioning

confidence: 99%

Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits

Tajalli¹,

Müller²,

Leblebici³

2007

Journal of Low Power Electronics

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Abstract-This article describes some techniques for implementing low-power clock and data recovery (CDR) circuits based on gated-oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient GO CDR are studied and based on that a top-down design methodology is introduced such that the jitter tolerance (JTOL) and frequency tolerance (FTOL) requirements of the system are simultaneously satisfied. A test chip has been implemented in standard digital 0.18 μm CMOS while the proposed CDR circuit consumes only 10.5 mW and occupies 0.045 mm 2 silicon area in 2.5 Gbps data bit rate. Measurement results show a good agreement to analyses proofs the capabilities of the proposed approach for implementing low-power GO CDRs.

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“…In our previous paper [30], we swept three critical Digital PLL (DPLL) parameters for the eye-tracking architecture [22]; i.e., the edge-detection interval of the BBPD, the number of clock phases and the phase update interval, in order to investigate their effects on the jitter tolerance of the DR circuit. The edge-detection interval for the DR circuit is a critical parameter of this design.…”

Section: Modified Dr Architecturementioning

confidence: 99%

“…In addition, we not only use one rotating phase as shown in Fig. 12(a) [22], but three rotating phases, a fixed distance apart (as seen in Fig. 12 (b)).…”

Section: Modified Dr Architecturementioning

confidence: 99%

Overview of oversampling clock and data recovery circuits

Ahmed

Kwaśniewski

Canadian Conference on Electrical and Computer Engineering, 2005.

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A 50-mW/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface With Digital Eye-Tracking

Cited by 32 publications

References 9 publications

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits

Overview of oversampling clock and data recovery circuits

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