Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits

Abstract

Abstract-This article describes some techniques for implementing low-power clock and data recovery (CDR) circuits based on gated-oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient GO CDR are studied and based on that a top-down design methodology is introduced such that the jitter tolerance (JTOL) and frequency tolerance (FTOL) requirements of the system are simultaneously satisfied. A test chip has been implemented in standard digital 0.18 μm CMOS while the proposed CDR circuit consumes only 10.5 mW and occupies 0.045 mm 2 silicon area in 2.5 Gbps data bit rate. Measurement results show a good agreement to analyses proofs the capabilities of the proposed approach for implementing low-power GO CDRs.